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authorLijian.Zhang <Lijian.Zhang@arm.com>2019-05-29 17:13:42 +0800
committerNeale Ranns <nranns@cisco.com>2019-06-26 11:38:59 +0000
commit0f9845120afb1dde120e2dac1ee0f280801307a4 (patch)
tree8f80c0432772dad988093a3bbe35e0e2148c6156 /src
parentc47b97ddacc35cb10e4a2b0dcfff3e690ec5bf76 (diff)
vppinfra: add u64x2_scatter/u32x4_scatter
Add u64x2_scatter/u32x4_scatter in vector_neon.h. u64x2_scatter/u32x4_scatter scatters data from SIMD register to scattered memory locations. Type: feature Change-Id: I298d5478c7ba6935ab7402a6d467c7ee00f17e9f Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com> Reviewed-by: Sirshak Das <Sirshak.Das@arm.com> Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
Diffstat (limited to 'src')
-rw-r--r--src/vppinfra/vector_neon.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/vppinfra/vector_neon.h b/src/vppinfra/vector_neon.h
index 4e911ac678a..e0d0f065c0e 100644
--- a/src/vppinfra/vector_neon.h
+++ b/src/vppinfra/vector_neon.h
@@ -160,6 +160,22 @@ u32x4_gather (void *p0, void *p1, void *p2, void *p3)
return r;
}
+static_always_inline void
+u64x2_scatter (u64x2 r, void *p0, void *p1)
+{
+ *(u64 *) p0 = vgetq_lane_u64 (r, 0);
+ *(u64 *) p1 = vgetq_lane_u64 (r, 1);
+}
+
+static_always_inline void
+u32x4_scatter (u32x4 r, void *p0, void *p1, void *p2, void *p3)
+{
+ *(u32 *) p0 = vgetq_lane_u32 (r, 0);
+ *(u32 *) p1 = vgetq_lane_u32 (r, 1);
+ *(u32 *) p2 = vgetq_lane_u32 (r, 2);
+ *(u32 *) p3 = vgetq_lane_u32 (r, 3);
+}
+
#define CLIB_HAVE_VEC128_MSB_MASK
#define CLIB_HAVE_VEC128_UNALIGNED_LOAD_STORE