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authorMarvin Liu <yong.liu@intel.com>2023-03-15 23:00:52 +0800
committerMarvin Liu <yong.liu@intel.com>2023-03-15 23:15:06 +0800
commit6a6df00abcb8dd98d4793f4dca114b97a7c48354 (patch)
tree2db8e6606cad70111bcf18051e95cd46d155c97a /src
parentf4ddf16eece8648f41b9b3491e4d972aeefb077f (diff)
dma_intel: fix potential invalid batch status
DMA batch status was set by hardware. Its value may be variable between cpus twice accesses. Saving the value of status can fix it. Type: fix Signed-off-by: Marvin Liu <yong.liu@intel.com> Change-Id: Ibc9337239555744a571685b486c986991c3e9b18
Diffstat (limited to 'src')
-rw-r--r--src/plugins/dma_intel/dsa.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/src/plugins/dma_intel/dsa.c b/src/plugins/dma_intel/dsa.c
index a1efcfaa42a..473f2efa93e 100644
--- a/src/plugins/dma_intel/dsa.c
+++ b/src/plugins/dma_intel/dsa.c
@@ -350,7 +350,7 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
intel_dsa_thread_t *t =
vec_elt_at_index (idm->dsa_threads, vm->thread_index);
u32 n_pending = 0, n = 0;
- u8 glitch = 0;
+ u8 glitch = 0, status;
if (!t->pending_batches)
return 0;
@@ -362,8 +362,9 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
intel_dsa_batch_t *b = t->pending_batches[i];
intel_dsa_channel_t *ch = b->ch;
- if ((b->status == INTEL_DSA_STATUS_SUCCESS ||
- b->status == INTEL_DSA_STATUS_CPU_SUCCESS) &&
+ status = b->status;
+ if ((status == INTEL_DSA_STATUS_SUCCESS ||
+ status == INTEL_DSA_STATUS_CPU_SUCCESS) &&
!glitch)
{
/* callback */
@@ -384,7 +385,7 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
vec_add1 (idm->dsa_config_heap[b->config_heap_index].freelist, b);
intel_dsa_channel_lock (ch);
- if (b->status == INTEL_DSA_STATUS_SUCCESS)
+ if (status == INTEL_DSA_STATUS_SUCCESS)
{
ch->n_enq--;
ch->completed++;
@@ -396,7 +397,7 @@ intel_dsa_node_fn (vlib_main_t *vm, vlib_node_runtime_t *node,
b->batch.n_enq = 0;
b->status = INTEL_DSA_STATUS_IDLE;
}
- else if (b->status == INTEL_DSA_STATUS_BUSY)
+ else if (status == INTEL_DSA_STATUS_BUSY)
{
glitch = 1 & b->barrier_before_last;
t->pending_batches[n++] = b;