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authorDamjan Marion <damarion@cisco.com>2018-06-26 16:05:43 +0200
committerDamjan Marion <dmarion@me.com>2018-06-26 15:11:22 +0000
commit13c98a2b220328b7273f6cb6189f190974a87701 (patch)
tree827993b4193bd955af3f7056eebea5d553e37cb1 /src
parent497deaf72f98dd104d9c9999a877ddd2f04c0aa6 (diff)
We don't have (yet) 128-bit unaligned load/store on ARM
Change-Id: I16395bbf843e338cdd366d85bb4df3de95d9b265 Signed-off-by: Damjan Marion <damarion@cisco.com>
Diffstat (limited to 'src')
-rw-r--r--src/vppinfra/bitmap.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vppinfra/bitmap.h b/src/vppinfra/bitmap.h
index 9418b1fcced..574f4c1b0a8 100644
--- a/src/vppinfra/bitmap.h
+++ b/src/vppinfra/bitmap.h
@@ -386,7 +386,7 @@ clib_bitmap_first_set (uword * ai)
{
uword i = 0;
#if uword_bits == 64
-#if defined (CLIB_HAVE_VEC256)
+#if defined(CLIB_HAVE_VEC256)
while (i + 7 < vec_len (ai))
{
u64x4 v;
@@ -395,7 +395,7 @@ clib_bitmap_first_set (uword * ai)
break;
i += 8;
}
-#elif defined (CLIB_HAVE_VEC128)
+#elif defined(CLIB_HAVE_VEC128) && defined(CLIB_HAVE_VEC128_UNALIGNED_LOAD_STORE)
while (i + 3 < vec_len (ai))
{
u64x2 v;