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| author |   Dave Barach <dave@barachs.net> | 2020-01-29 18:05:24 -0500 |
|---|---|---|
| committer |   Florin Coras <florin.coras@gmail.com> | 2020-01-30 20:45:18 +0000 |
| commit | c25048bd05a319511aa7386f75e1fae2b2a623c4 (patch) | |
| tree | 4254d34aba20058eb04213ffe4ab738f0dc250fd /test/test_sixrd.py | |
| parent | 91592c0c9cdd1bc61a2796e41a8becc30aaf8082 (diff) | |
vppinfra: improve clocks_per_second convergence
Apply exponential smoothing to the clock rate update calculation in
clib_time_verify_frequency(), with a half-life of 1 minute and a
sampling frequency of 16 seconds. Within 5 minutes or so, the
calculation converges
With each rate recalculation: reset total_cpu_time based on the kernel
timebase delta since vpp started, and the new clock rate
Improve the "show clock [verbose]" debug CLI command.
BFD echo + echo fail tests marked off until the BFD code can be
reworked a bit.
Type: fix
Signed-off-by: Dave Barach <dave@barachs.net>
Change-Id: I24e88a78819b12867736c875067b386ef6115c5c
Diffstat (limited to 'test/test_sixrd.py')
0 files changed, 0 insertions, 0 deletions