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| author |   Zhiyong Yang <zhiyong.yang@intel.com> | 2019-05-21 01:46:35 -0400 |
|---|---|---|
| committer |   Damjan Marion <dmarion@me.com> | 2019-05-21 14:13:48 +0000 |
| commit | d3ebc83af33be72409032e7969dc2dcfc07a9783 (patch) | |
| tree | 896bc90ee352b55c2dc3b524994be046598563d9 /test/test_srv6_as.py | |
| parent | 46cd9fc970e6a17457be497db71c681d3eaa3087 (diff) | |
geneve_input: leverage vlib_get_buffers
vlib_get_buffers helps save 1.4 clocks/pkt from 34.6 to 33.2
clocks/pkt on Skylake.
Change-Id: I741d10d20373f12d30ec8b04ad8c7444ffb42246
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
Diffstat (limited to 'test/test_srv6_as.py')
0 files changed, 0 insertions, 0 deletions