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| author |   Zhiyong Yang <zhiyong.yang@intel.com> | 2018-11-05 03:45:25 -0500 |
|---|---|---|
| committer |   John Lo <loj@cisco.com> | 2018-11-05 21:02:38 +0000 |
| commit | b0073e276d9e12f02f8f9874fd09ae532a0baa47 (patch) | |
| tree | f2db5ddcf53e9bc48421a6ff82cbee0fcbe75f2d /test/test_vcl.py | |
| parent | 2130284302788759c7b2644efb801b84411e342e (diff) | |
vxlan: prefetch extra one cacheline holding external header
For vxlan_encap, code will touch memory area before the field "data"
in struct vlib_buffer_t, however so far it is not prefetched in cache
yet for this graph node.
After applying the patch, 2~3 cycles per pkt for vxlan4_encap can be
saved on Haswell. It will bring a lot of benefits on DVN platform too.
Change-Id: I26d8c57fb3d2415726be5367117d73eb715e35ad
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
Diffstat (limited to 'test/test_vcl.py')
0 files changed, 0 insertions, 0 deletions