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| author |   Jieqiang Wang <jieqiang.wang@arm.com> | 2022-11-25 15:26:55 +0800 |
|---|---|---|
| committer |   Beno�t Ganne <bganne@cisco.com> | 2022-11-29 12:58:51 +0000 |
| commit | 6db2758611dd5f1cf82c0bf78cfb95230ed2786f (patch) | |
| tree | e150ae122bf34db9ae17231c5a74a831fdc1e582 /test/test_wireguard.py | |
| parent | 520cde406797eb076591797fbf9978b959e6cf17 (diff) | |
rdma: fix for-loop initialization in scalar path
When n_rx_packets is less then 16(VEC256) or 8(VEC128), code execution
will fall into scalar path of processing packets. But with a wrong
initialization value for n_left set to zero, i in the for-loop will
equal to n_rx_packets. This leads to the bypass of required ip4 checksum
validation and byte count endianness conversion in scalar path.
Besides, refactor the code using while instead of for-loop to keep
consistency with VPP code style.
Type: fix
Fixes: bf93670c515d ("rdma: fix ipv4 checksum check in rdma-input node")
Signed-off-by: Lijian Zhang <lijian.zhang@arm.com>
Signed-off-by: Jieqiang Wang <jieqiang.wang@arm.com>
Change-Id: Ib4e8cb5202735f8b060c99caddf26035657551e1
Diffstat (limited to 'test/test_wireguard.py')
0 files changed, 0 insertions, 0 deletions