diff options
Diffstat (limited to 'vnet/vnet/devices/nic/ixge.h')
| -rw-r--r-- | vnet/vnet/devices/nic/ixge.h | 510 |
1 files changed, 281 insertions, 229 deletions
diff --git a/vnet/vnet/devices/nic/ixge.h b/vnet/vnet/devices/nic/ixge.h index 8062b8c8a97..a8e652dcdab 100644 --- a/vnet/vnet/devices/nic/ixge.h +++ b/vnet/vnet/devices/nic/ixge.h @@ -23,7 +23,8 @@ #include <vnet/ip/ip4_packet.h> #include <vnet/ip/ip6_packet.h> -typedef volatile struct { +typedef volatile struct +{ /* [31:7] 128 byte aligned. */ u32 descriptor_address[2]; u32 n_descriptor_bytes; @@ -50,7 +51,7 @@ typedef volatile struct { u32 rx_split_control; u32 tail_index; - CLIB_PAD_FROM_TO (0x1c, 0x28); + CLIB_PAD_FROM_TO (0x1c, 0x28); /* [7:0] rx/tx prefetch threshold [15:8] rx/tx host threshold @@ -62,15 +63,18 @@ typedef volatile struct { u32 rx_coallesce_control; - union { - struct { + union + { + struct + { /* packets bytes lo hi */ u32 stats[3]; u32 unused; } rx; - struct { + struct + { u32 unused[2]; /* [0] enables head write back. */ @@ -80,12 +84,14 @@ typedef volatile struct { } ixge_dma_regs_t; /* Only advanced descriptors are supported. */ -typedef struct { +typedef struct +{ u64 tail_address; u64 head_address; } ixge_rx_to_hw_descriptor_t; -typedef struct { +typedef struct +{ u32 status[3]; u16 n_packet_bytes_this_descriptor; u16 vlan_tag; @@ -117,7 +123,8 @@ typedef struct { /* For layer2 packets stats0 bottom 3 bits give ether type index from filter. */ #define IXGE_RX_DESCRIPTOR_STATUS0_LAYER2_ETHERNET_TYPE(s) ((s) & 7) -typedef struct { +typedef struct +{ u64 buffer_address; u16 n_bytes_this_buffer; u16 status0; @@ -138,8 +145,10 @@ typedef struct { #define IXGE_TX_DESCRIPTOR_STATUS1_N_BYTES_IN_PACKET(l) ((l) << 14) } ixge_tx_descriptor_t; -typedef struct { - struct { +typedef struct +{ + struct + { u8 checksum_start_offset; u8 checksum_insert_offset; u16 checksum_end_offset; @@ -154,14 +163,16 @@ typedef struct { u16 max_tcp_segment_size; } __attribute__ ((packed)) ixge_tx_context_descriptor_t; -typedef union { +typedef union +{ ixge_rx_to_hw_descriptor_t rx_to_hw; ixge_rx_from_hw_descriptor_t rx_from_hw; ixge_tx_descriptor_t tx; u32x4 as_u32x4; } ixge_descriptor_t; -typedef volatile struct { +typedef volatile struct +{ /* [2] pcie master disable [3] mac reset [26] global device reset */ @@ -173,56 +184,58 @@ typedef volatile struct { [18] io active [19] pcie master enable status */ u32 status_read_only; - CLIB_PAD_FROM_TO (0xc, 0x18); + CLIB_PAD_FROM_TO (0xc, 0x18); /* [14] pf reset done [17] relaxed ordering disable [26] extended vlan enable [28] driver loaded */ u32 extended_control; - CLIB_PAD_FROM_TO (0x1c, 0x20); + CLIB_PAD_FROM_TO (0x1c, 0x20); /* software definable pins. sdp_data [7:0] sdp_is_output [15:8] sdp_is_native [23:16] sdp_function [31:24]. - */ + */ u32 sdp_control; - CLIB_PAD_FROM_TO (0x24, 0x28); + CLIB_PAD_FROM_TO (0x24, 0x28); /* [0] i2c clock in [1] i2c clock out [2] i2c data in [3] i2c data out */ u32 i2c_control; - CLIB_PAD_FROM_TO (0x2c, 0x4c); + CLIB_PAD_FROM_TO (0x2c, 0x4c); u32 tcp_timer; - CLIB_PAD_FROM_TO (0x50, 0x200); + CLIB_PAD_FROM_TO (0x50, 0x200); u32 led_control; - CLIB_PAD_FROM_TO (0x204, 0x600); + CLIB_PAD_FROM_TO (0x204, 0x600); u32 core_spare; - CLIB_PAD_FROM_TO (0x604, 0x700); + CLIB_PAD_FROM_TO (0x604, 0x700); - struct { + struct + { u32 vflr_events_clear[4]; u32 mailbox_interrupt_status[4]; u32 mailbox_interrupt_enable[4]; - CLIB_PAD_FROM_TO (0x730, 0x800); + CLIB_PAD_FROM_TO (0x730, 0x800); } pf_foo; - struct { + struct + { u32 status_write_1_to_clear; - CLIB_PAD_FROM_TO (0x804, 0x808); + CLIB_PAD_FROM_TO (0x804, 0x808); u32 status_write_1_to_set; - CLIB_PAD_FROM_TO (0x80c, 0x810); + CLIB_PAD_FROM_TO (0x80c, 0x810); u32 status_auto_clear_enable; - CLIB_PAD_FROM_TO (0x814, 0x820); + CLIB_PAD_FROM_TO (0x814, 0x820); /* [11:3] minimum inter-interrupt interval - (2e-6 units; 20e-6 units for fast ethernet). + (2e-6 units; 20e-6 units for fast ethernet). [15] low-latency interrupt moderation enable [20:16] low-latency interrupt credit [27:21] interval counter @@ -230,9 +243,9 @@ typedef volatile struct { u32 throttle0[24]; u32 enable_write_1_to_set; - CLIB_PAD_FROM_TO (0x884, 0x888); + CLIB_PAD_FROM_TO (0x884, 0x888); u32 enable_write_1_to_clear; - CLIB_PAD_FROM_TO (0x88c, 0x890); + CLIB_PAD_FROM_TO (0x88c, 0x890); u32 enable_auto_clear; u32 msi_to_eitr_select; /* [3:0] spd 0-3 interrupt detection enable @@ -240,88 +253,89 @@ typedef volatile struct { [5] other clear disable (makes other bits in status not clear on read) etc. */ u32 control; - CLIB_PAD_FROM_TO (0x89c, 0x900); + CLIB_PAD_FROM_TO (0x89c, 0x900); /* Defines interrupt mapping for 128 rx + 128 tx queues. 64 x 4 8 bit entries. For register [i]: - [5:0] bit in interrupt status for rx queue 2*i + 0 - [7] valid bit - [13:8] bit for tx queue 2*i + 0 - [15] valid bit - similar for rx 2*i + 1 and tx 2*i + 1. */ + [5:0] bit in interrupt status for rx queue 2*i + 0 + [7] valid bit + [13:8] bit for tx queue 2*i + 0 + [15] valid bit + similar for rx 2*i + 1 and tx 2*i + 1. */ u32 queue_mapping[64]; /* tcp timer [7:0] and other interrupts [15:8] */ u32 misc_mapping; - CLIB_PAD_FROM_TO (0xa04, 0xa90); + CLIB_PAD_FROM_TO (0xa04, 0xa90); /* 64 interrupts determined by mappings. */ u32 status1_write_1_to_clear[4]; u32 enable1_write_1_to_set[4]; u32 enable1_write_1_to_clear[4]; - CLIB_PAD_FROM_TO (0xac0, 0xad0); + CLIB_PAD_FROM_TO (0xac0, 0xad0); u32 status1_enable_auto_clear[4]; - CLIB_PAD_FROM_TO (0xae0, 0x1000); + CLIB_PAD_FROM_TO (0xae0, 0x1000); } interrupt; ixge_dma_regs_t rx_dma0[64]; - CLIB_PAD_FROM_TO (0x2000, 0x2140); + CLIB_PAD_FROM_TO (0x2000, 0x2140); u32 dcb_rx_packet_plane_t4_config[8]; u32 dcb_rx_packet_plane_t4_status[8]; - CLIB_PAD_FROM_TO (0x2180, 0x2300); + CLIB_PAD_FROM_TO (0x2180, 0x2300); /* reg i defines mapping for 4 rx queues starting at 4*i + 0. */ u32 rx_queue_stats_mapping[32]; u32 rx_queue_stats_control; - CLIB_PAD_FROM_TO (0x2384, 0x2410); + CLIB_PAD_FROM_TO (0x2384, 0x2410); u32 fc_user_descriptor_ptr[2]; u32 fc_buffer_control; - CLIB_PAD_FROM_TO (0x241c, 0x2420); + CLIB_PAD_FROM_TO (0x241c, 0x2420); u32 fc_rx_dma; - CLIB_PAD_FROM_TO (0x2424, 0x2430); + CLIB_PAD_FROM_TO (0x2424, 0x2430); u32 dcb_packet_plane_control; - CLIB_PAD_FROM_TO (0x2434, 0x2f00); + CLIB_PAD_FROM_TO (0x2434, 0x2f00); u32 rx_dma_control; u32 pf_queue_drop_enable; - CLIB_PAD_FROM_TO (0x2f08, 0x2f20); + CLIB_PAD_FROM_TO (0x2f08, 0x2f20); u32 rx_dma_descriptor_cache_config; - CLIB_PAD_FROM_TO (0x2f24, 0x3000); + CLIB_PAD_FROM_TO (0x2f24, 0x3000); /* 1 bit. */ u32 rx_enable; - CLIB_PAD_FROM_TO (0x3004, 0x3008); + CLIB_PAD_FROM_TO (0x3004, 0x3008); /* [15:0] ether type (little endian) [31:16] opcode (big endian) */ u32 flow_control_control; - CLIB_PAD_FROM_TO (0x300c, 0x3020); + CLIB_PAD_FROM_TO (0x300c, 0x3020); /* 3 bit traffic class for each of 8 priorities. */ u32 rx_priority_to_traffic_class; - CLIB_PAD_FROM_TO (0x3024, 0x3028); + CLIB_PAD_FROM_TO (0x3024, 0x3028); u32 rx_coallesce_data_buffer_control; - CLIB_PAD_FROM_TO (0x302c, 0x3190); + CLIB_PAD_FROM_TO (0x302c, 0x3190); u32 rx_packet_buffer_flush_detect; - CLIB_PAD_FROM_TO (0x3194, 0x3200); - u32 flow_control_tx_timers[4]; /* 2 timer values */ - CLIB_PAD_FROM_TO (0x3210, 0x3220); + CLIB_PAD_FROM_TO (0x3194, 0x3200); + u32 flow_control_tx_timers[4]; /* 2 timer values */ + CLIB_PAD_FROM_TO (0x3210, 0x3220); u32 flow_control_rx_threshold_lo[8]; - CLIB_PAD_FROM_TO (0x3240, 0x3260); + CLIB_PAD_FROM_TO (0x3240, 0x3260); u32 flow_control_rx_threshold_hi[8]; - CLIB_PAD_FROM_TO (0x3280, 0x32a0); + CLIB_PAD_FROM_TO (0x3280, 0x32a0); u32 flow_control_refresh_threshold; - CLIB_PAD_FROM_TO (0x32a4, 0x3c00); + CLIB_PAD_FROM_TO (0x32a4, 0x3c00); /* For each of 8 traffic classes (units of bytes). */ u32 rx_packet_buffer_size[8]; - CLIB_PAD_FROM_TO (0x3c20, 0x3d00); + CLIB_PAD_FROM_TO (0x3c20, 0x3d00); u32 flow_control_config; - CLIB_PAD_FROM_TO (0x3d04, 0x4200); + CLIB_PAD_FROM_TO (0x3d04, 0x4200); - struct { + struct + { u32 pcs_config; - CLIB_PAD_FROM_TO (0x4204, 0x4208); + CLIB_PAD_FROM_TO (0x4204, 0x4208); u32 link_control; u32 link_status; u32 pcs_debug[2]; @@ -329,10 +343,11 @@ typedef volatile struct { u32 link_partner_ability; u32 auto_negotiation_tx_next_page; u32 auto_negotiation_link_partner_next_page; - CLIB_PAD_FROM_TO (0x4228, 0x4240); + CLIB_PAD_FROM_TO (0x4228, 0x4240); } gige_mac; - struct { + struct + { /* [0] tx crc enable [2] enable frames up to max frame size register [31:16] [10] pad frames < 64 bytes if specified by user @@ -349,25 +364,25 @@ typedef volatile struct { u32 status; u32 pause_and_pace_control; - CLIB_PAD_FROM_TO (0x424c, 0x425c); + CLIB_PAD_FROM_TO (0x424c, 0x425c); u32 phy_command; u32 phy_data; - CLIB_PAD_FROM_TO (0x4264, 0x4268); + CLIB_PAD_FROM_TO (0x4264, 0x4268); /* [31:16] max frame size in bytes. */ u32 rx_max_frame_size; - CLIB_PAD_FROM_TO (0x426c, 0x4288); + CLIB_PAD_FROM_TO (0x426c, 0x4288); /* [0] - [2] pcs receive link up? (latch lo) - [7] local fault + [2] pcs receive link up? (latch lo) + [7] local fault [1] - [0] pcs 10g base r capable - [1] pcs 10g base x capable - [2] pcs 10g base w capable - [10] rx local fault - [11] tx local fault - [15:14] 2 => device present at this address (else not present) */ + [0] pcs 10g base r capable + [1] pcs 10g base x capable + [2] pcs 10g base w capable + [10] rx local fault + [11] tx local fault + [15:14] 2 => device present at this address (else not present) */ u32 xgxs_status[2]; u32 base_x_pcs_status; @@ -397,14 +412,14 @@ typedef volatile struct { [11] restart autoneg on transition to dx power state [12] restart autoneg [15:13] link mode: - 0 => 1g no autoneg - 1 => 10g kx4 parallel link no autoneg - 2 => 1g bx autoneg - 3 => 10g sfi serdes - 4 => kx4/kx/kr - 5 => xgmii 1g/100m - 6 => kx4/kx/kr 1g an - 7 kx4/kx/kr sgmii. + 0 => 1g no autoneg + 1 => 10g kx4 parallel link no autoneg + 2 => 1g bx autoneg + 3 => 10g sfi serdes + 4 => kx4/kx/kr + 5 => xgmii 1g/100m + 6 => kx4/kx/kr 1g an + 7 kx4/kx/kr sgmii. [16] kr support [17] fec requested [18] fec ability @@ -432,99 +447,100 @@ typedef volatile struct { [24] 10g kr pcs enabled [25] sgmii enabled [27:26] mac link mode - 0 => 1g - 1 => 10g parallel - 2 => 10g serial - 3 => autoneg + 0 => 1g + 1 => 10g parallel + 2 => 10g serial + 3 => autoneg [29:28] link speed - 1 => 100m - 2 => 1g - 3 => 10g + 1 => 100m + 2 => 1g + 3 => 10g [30] link is up [31] kx/kx4/kr backplane autoneg completed successfully. */ u32 link_status; /* [17:16] pma/pmd for 10g serial - 0 => kr, 2 => sfi + 0 => kr, 2 => sfi [18] disable dme pages */ u32 auto_negotiation_control2; - CLIB_PAD_FROM_TO (0x42ac, 0x42b0); + CLIB_PAD_FROM_TO (0x42ac, 0x42b0); u32 link_partner_ability[2]; - CLIB_PAD_FROM_TO (0x42b8, 0x42d0); + CLIB_PAD_FROM_TO (0x42b8, 0x42d0); u32 manageability_control; u32 link_partner_next_page[2]; - CLIB_PAD_FROM_TO (0x42dc, 0x42e0); + CLIB_PAD_FROM_TO (0x42dc, 0x42e0); u32 kr_pcs_control; u32 kr_pcs_status; u32 fec_status[2]; - CLIB_PAD_FROM_TO (0x42f0, 0x4314); + CLIB_PAD_FROM_TO (0x42f0, 0x4314); u32 sgmii_control; - CLIB_PAD_FROM_TO (0x4318, 0x4324); + CLIB_PAD_FROM_TO (0x4318, 0x4324); u32 link_status2; - CLIB_PAD_FROM_TO (0x4328, 0x4900); + CLIB_PAD_FROM_TO (0x4328, 0x4900); } xge_mac; u32 tx_dcb_control; u32 tx_dcb_descriptor_plane_queue_select; u32 tx_dcb_descriptor_plane_t1_config; u32 tx_dcb_descriptor_plane_t1_status; - CLIB_PAD_FROM_TO (0x4910, 0x4950); + CLIB_PAD_FROM_TO (0x4910, 0x4950); /* For each TC in units of 1k bytes. */ u32 tx_packet_buffer_thresholds[8]; - CLIB_PAD_FROM_TO (0x4970, 0x4980); - struct { + CLIB_PAD_FROM_TO (0x4970, 0x4980); + struct + { u32 mmw; u32 config; u32 status; u32 rate_drift; } dcb_tx_rate_scheduler; - CLIB_PAD_FROM_TO (0x4990, 0x4a80); + CLIB_PAD_FROM_TO (0x4990, 0x4a80); u32 tx_dma_control; - CLIB_PAD_FROM_TO (0x4a84, 0x4a88); + CLIB_PAD_FROM_TO (0x4a84, 0x4a88); u32 tx_dma_tcp_flags_control[2]; - CLIB_PAD_FROM_TO (0x4a90, 0x4b00); + CLIB_PAD_FROM_TO (0x4a90, 0x4b00); u32 pf_mailbox[64]; - CLIB_PAD_FROM_TO (0x4c00, 0x5000); + CLIB_PAD_FROM_TO (0x4c00, 0x5000); /* RX */ u32 checksum_control; - CLIB_PAD_FROM_TO (0x5004, 0x5008); + CLIB_PAD_FROM_TO (0x5004, 0x5008); u32 rx_filter_control; - CLIB_PAD_FROM_TO (0x500c, 0x5010); + CLIB_PAD_FROM_TO (0x500c, 0x5010); u32 management_vlan_tag[8]; u32 management_udp_tcp_ports[8]; - CLIB_PAD_FROM_TO (0x5050, 0x5078); + CLIB_PAD_FROM_TO (0x5050, 0x5078); /* little endian. */ u32 extended_vlan_ether_type; - CLIB_PAD_FROM_TO (0x507c, 0x5080); + CLIB_PAD_FROM_TO (0x507c, 0x5080); /* [1] store/dma bad packets [8] accept all multicast [9] accept all unicast [10] accept all broadcast. */ u32 filter_control; - CLIB_PAD_FROM_TO (0x5084, 0x5088); + CLIB_PAD_FROM_TO (0x5084, 0x5088); /* [15:0] vlan ethernet type (0x8100) little endian [28] cfi bit expected [29] drop packets with unexpected cfi bit [30] vlan filter enable. */ u32 vlan_control; - CLIB_PAD_FROM_TO (0x508c, 0x5090); + CLIB_PAD_FROM_TO (0x508c, 0x5090); /* [1:0] hi bit of ethernet address for 12 bit index into multicast table - 0 => 47, 1 => 46, 2 => 45, 3 => 43. + 0 => 47, 1 => 46, 2 => 45, 3 => 43. [2] enable multicast filter */ u32 multicast_control; - CLIB_PAD_FROM_TO (0x5094, 0x5100); + CLIB_PAD_FROM_TO (0x5094, 0x5100); u32 fcoe_rx_control; - CLIB_PAD_FROM_TO (0x5104, 0x5108); + CLIB_PAD_FROM_TO (0x5104, 0x5108); u32 fc_flt_context; - CLIB_PAD_FROM_TO (0x510c, 0x5110); + CLIB_PAD_FROM_TO (0x510c, 0x5110); u32 fc_filter_control; - CLIB_PAD_FROM_TO (0x5114, 0x5120); + CLIB_PAD_FROM_TO (0x5114, 0x5120); u32 rx_message_type_lo; - CLIB_PAD_FROM_TO (0x5124, 0x5128); + CLIB_PAD_FROM_TO (0x5124, 0x5128); /* [15:0] ethernet type (little endian) [18:16] matche pri in vlan tag [19] priority match enable @@ -535,50 +551,50 @@ typedef volatile struct { [31] filter enable. (See ethernet_type_queue_select.) */ u32 ethernet_type_queue_filter[8]; - CLIB_PAD_FROM_TO (0x5148, 0x5160); + CLIB_PAD_FROM_TO (0x5148, 0x5160); /* [7:0] l2 ethernet type and [15:8] l2 ethernet type or */ u32 management_decision_filters1[8]; u32 vf_vm_tx_switch_loopback_enable[2]; u32 rx_time_sync_control; - CLIB_PAD_FROM_TO (0x518c, 0x5190); + CLIB_PAD_FROM_TO (0x518c, 0x5190); u32 management_ethernet_type_filters[4]; u32 rx_timestamp_attributes_lo; u32 rx_timestamp_hi; u32 rx_timestamp_attributes_hi; - CLIB_PAD_FROM_TO (0x51ac, 0x51b0); + CLIB_PAD_FROM_TO (0x51ac, 0x51b0); u32 pf_virtual_control; - CLIB_PAD_FROM_TO (0x51b4, 0x51d8); + CLIB_PAD_FROM_TO (0x51b4, 0x51d8); u32 fc_offset_parameter; - CLIB_PAD_FROM_TO (0x51dc, 0x51e0); + CLIB_PAD_FROM_TO (0x51dc, 0x51e0); u32 vf_rx_enable[2]; u32 rx_timestamp_lo; - CLIB_PAD_FROM_TO (0x51ec, 0x5200); + CLIB_PAD_FROM_TO (0x51ec, 0x5200); /* 12 bits determined by multicast_control lookup bits in this vector. */ u32 multicast_enable[128]; /* [0] ethernet address [31:0] [1] [15:0] ethernet address [47:32] - [31] valid bit. + [31] valid bit. Index 0 is read from eeprom after reset. */ u32 rx_ethernet_address0[16][2]; - CLIB_PAD_FROM_TO (0x5480, 0x5800); + CLIB_PAD_FROM_TO (0x5480, 0x5800); u32 wake_up_control; - CLIB_PAD_FROM_TO (0x5804, 0x5808); + CLIB_PAD_FROM_TO (0x5804, 0x5808); u32 wake_up_filter_control; - CLIB_PAD_FROM_TO (0x580c, 0x5818); + CLIB_PAD_FROM_TO (0x580c, 0x5818); u32 multiple_rx_queue_command_82598; - CLIB_PAD_FROM_TO (0x581c, 0x5820); + CLIB_PAD_FROM_TO (0x581c, 0x5820); u32 management_control; u32 management_filter_control; - CLIB_PAD_FROM_TO (0x5828, 0x5838); + CLIB_PAD_FROM_TO (0x5828, 0x5838); u32 wake_up_ip4_address_valid; - CLIB_PAD_FROM_TO (0x583c, 0x5840); + CLIB_PAD_FROM_TO (0x583c, 0x5840); u32 wake_up_ip4_address_table[4]; u32 management_control_to_host; - CLIB_PAD_FROM_TO (0x5854, 0x5880); + CLIB_PAD_FROM_TO (0x5854, 0x5880); u32 wake_up_ip6_address_table[4]; /* unicast_and broadcast_and vlan_and ip_address_and @@ -586,55 +602,58 @@ typedef volatile struct { u32 management_decision_filters[8]; u32 management_ip4_or_ip6_address_filters[4][4]; - CLIB_PAD_FROM_TO (0x58f0, 0x5900); + CLIB_PAD_FROM_TO (0x58f0, 0x5900); u32 wake_up_packet_length; - CLIB_PAD_FROM_TO (0x5904, 0x5910); + CLIB_PAD_FROM_TO (0x5904, 0x5910); u32 management_ethernet_address_filters[4][2]; - CLIB_PAD_FROM_TO (0x5930, 0x5a00); + CLIB_PAD_FROM_TO (0x5930, 0x5a00); u32 wake_up_packet_memory[32]; - CLIB_PAD_FROM_TO (0x5a80, 0x5c00); + CLIB_PAD_FROM_TO (0x5a80, 0x5c00); u32 redirection_table_82598[32]; u32 rss_random_keys_82598[10]; - CLIB_PAD_FROM_TO (0x5ca8, 0x6000); + CLIB_PAD_FROM_TO (0x5ca8, 0x6000); ixge_dma_regs_t tx_dma[128]; u32 pf_vm_vlan_insert[64]; u32 tx_dma_tcp_max_alloc_size_requests; - CLIB_PAD_FROM_TO (0x8104, 0x8110); + CLIB_PAD_FROM_TO (0x8104, 0x8110); u32 vf_tx_enable[2]; - CLIB_PAD_FROM_TO (0x8118, 0x8120); + CLIB_PAD_FROM_TO (0x8118, 0x8120); /* [0] dcb mode enable [1] virtualization mode enable [3:2] number of tcs/qs per pool. */ u32 multiple_tx_queues_command; - CLIB_PAD_FROM_TO (0x8124, 0x8200); + CLIB_PAD_FROM_TO (0x8124, 0x8200); u32 pf_vf_anti_spoof[8]; u32 pf_dma_tx_switch_control; - CLIB_PAD_FROM_TO (0x8224, 0x82e0); + CLIB_PAD_FROM_TO (0x8224, 0x82e0); u32 tx_strict_low_latency_queues[4]; - CLIB_PAD_FROM_TO (0x82f0, 0x8600); + CLIB_PAD_FROM_TO (0x82f0, 0x8600); u32 tx_queue_stats_mapping_82599[32]; u32 tx_queue_packet_counts[32]; u32 tx_queue_byte_counts[32][2]; - struct { + struct + { u32 control; u32 status; u32 buffer_almost_full; - CLIB_PAD_FROM_TO (0x880c, 0x8810); + CLIB_PAD_FROM_TO (0x880c, 0x8810); u32 buffer_min_ifg; - CLIB_PAD_FROM_TO (0x8814, 0x8900); + CLIB_PAD_FROM_TO (0x8814, 0x8900); } tx_security; - struct { + struct + { u32 index; u32 salt; u32 key[4]; - CLIB_PAD_FROM_TO (0x8918, 0x8a00); + CLIB_PAD_FROM_TO (0x8918, 0x8a00); } tx_ipsec; - struct { + struct + { u32 capabilities; u32 control; u32 tx_sci[2]; @@ -644,10 +663,11 @@ typedef volatile struct { /* untagged packets, encrypted packets, protected packets, encrypted bytes, protected bytes */ u32 stats[5]; - CLIB_PAD_FROM_TO (0x8a50, 0x8c00); + CLIB_PAD_FROM_TO (0x8a50, 0x8c00); } tx_link_security; - struct { + struct + { u32 control; u32 timestamp_value[2]; u32 system_time[2]; @@ -655,18 +675,20 @@ typedef volatile struct { u32 time_adjustment_offset[2]; u32 aux_control; u32 target_time[2][2]; - CLIB_PAD_FROM_TO (0x8c34, 0x8c3c); + CLIB_PAD_FROM_TO (0x8c34, 0x8c3c); u32 aux_time_stamp[2][2]; - CLIB_PAD_FROM_TO (0x8c4c, 0x8d00); + CLIB_PAD_FROM_TO (0x8c4c, 0x8d00); } tx_timesync; - struct { + struct + { u32 control; u32 status; - CLIB_PAD_FROM_TO (0x8d08, 0x8e00); + CLIB_PAD_FROM_TO (0x8d08, 0x8e00); } rx_security; - struct { + struct + { u32 index; u32 ip_address[4]; u32 spi; @@ -674,10 +696,11 @@ typedef volatile struct { u32 key[4]; u32 salt; u32 mode; - CLIB_PAD_FROM_TO (0x8e34, 0x8f00); + CLIB_PAD_FROM_TO (0x8e34, 0x8f00); } rx_ipsec; - struct { + struct + { u32 capabilities; u32 control; u32 sci[2]; @@ -686,12 +709,12 @@ typedef volatile struct { u32 key[2][4]; /* see datasheet */ u32 stats[17]; - CLIB_PAD_FROM_TO (0x8f84, 0x9000); + CLIB_PAD_FROM_TO (0x8f84, 0x9000); } rx_link_security; /* 4 wake up, 2 management, 2 wake up. */ u32 flexible_filters[8][16][4]; - CLIB_PAD_FROM_TO (0x9800, 0xa000); + CLIB_PAD_FROM_TO (0x9800, 0xa000); /* 4096 bits. */ u32 vlan_filter[128]; @@ -704,26 +727,27 @@ typedef volatile struct { /* select one of 64 pools for each rx address. */ u32 rx_ethernet_address_pool_select[128][2]; - CLIB_PAD_FROM_TO (0xaa00, 0xc800); + CLIB_PAD_FROM_TO (0xaa00, 0xc800); u32 tx_priority_to_traffic_class; - CLIB_PAD_FROM_TO (0xc804, 0xcc00); + CLIB_PAD_FROM_TO (0xc804, 0xcc00); /* In bytes units of 1k. Total packet buffer is 160k. */ u32 tx_packet_buffer_size[8]; - CLIB_PAD_FROM_TO (0xcc20, 0xcd10); + CLIB_PAD_FROM_TO (0xcc20, 0xcd10); u32 tx_manageability_tc_mapping; - CLIB_PAD_FROM_TO (0xcd14, 0xcd20); + CLIB_PAD_FROM_TO (0xcd14, 0xcd20); u32 dcb_tx_packet_plane_t2_config[8]; u32 dcb_tx_packet_plane_t2_status[8]; - CLIB_PAD_FROM_TO (0xcd60, 0xce00); + CLIB_PAD_FROM_TO (0xcd60, 0xce00); u32 tx_flow_control_status; - CLIB_PAD_FROM_TO (0xce04, 0xd000); + CLIB_PAD_FROM_TO (0xce04, 0xd000); ixge_dma_regs_t rx_dma1[64]; - struct { + struct + { /* Bigendian ip4 src/dst address. */ u32 src_address[128]; u32 dst_address[128]; @@ -750,36 +774,38 @@ typedef volatile struct { u32 interrupt[128]; } ip4_filters; - CLIB_PAD_FROM_TO (0xea00, 0xeb00); + CLIB_PAD_FROM_TO (0xea00, 0xeb00); /* 4 bit rss output index indexed by 7 bit hash. 128 8 bit fields = 32 registers. */ u32 redirection_table_82599[32]; u32 rss_random_key_82599[10]; - CLIB_PAD_FROM_TO (0xeba8, 0xec00); + CLIB_PAD_FROM_TO (0xeba8, 0xec00); /* [15:0] reserved [22:16] rx queue index [29] low-latency interrupt on match [31] enable */ u32 ethernet_type_queue_select[8]; - CLIB_PAD_FROM_TO (0xec20, 0xec30); + CLIB_PAD_FROM_TO (0xec20, 0xec30); u32 syn_packet_queue_filter; - CLIB_PAD_FROM_TO (0xec34, 0xec60); + CLIB_PAD_FROM_TO (0xec34, 0xec60); u32 immediate_interrupt_rx_vlan_priority; - CLIB_PAD_FROM_TO (0xec64, 0xec70); + CLIB_PAD_FROM_TO (0xec64, 0xec70); u32 rss_queues_per_traffic_class; - CLIB_PAD_FROM_TO (0xec74, 0xec90); + CLIB_PAD_FROM_TO (0xec74, 0xec90); u32 lli_size_threshold; - CLIB_PAD_FROM_TO (0xec94, 0xed00); + CLIB_PAD_FROM_TO (0xec94, 0xed00); - struct { + struct + { u32 control; - CLIB_PAD_FROM_TO (0xed04, 0xed10); + CLIB_PAD_FROM_TO (0xed04, 0xed10); u32 table[8]; - CLIB_PAD_FROM_TO (0xed30, 0xee00); + CLIB_PAD_FROM_TO (0xed30, 0xee00); } fcoe_redirection; - struct { + struct + { /* [1:0] packet buffer allocation 0 => disabled, else 64k*2^(f-1) [3] packet buffer initialization done [4] perfetch match mode @@ -790,7 +816,7 @@ typedef volatile struct { [27:24] max linked list length [31:28] full threshold. */ u32 control; - CLIB_PAD_FROM_TO (0xee04, 0xee0c); + CLIB_PAD_FROM_TO (0xee04, 0xee0c); u32 data[8]; @@ -810,7 +836,7 @@ typedef volatile struct { [29:24] pool. */ u32 command; - CLIB_PAD_FROM_TO (0xee30, 0xee3c); + CLIB_PAD_FROM_TO (0xee30, 0xee3c); /* ip4 dst/src address, tcp ports, udp ports. set bits mean bit is ignored. */ u32 ip4_masks[4]; @@ -819,7 +845,7 @@ typedef volatile struct { u32 failed_usage_stats; u32 filters_match_stats; u32 filters_miss_stats; - CLIB_PAD_FROM_TO (0xee60, 0xee68); + CLIB_PAD_FROM_TO (0xee60, 0xee68); /* Lookup, signature. */ u32 hash_keys[2]; /* [15:0] ip6 src address 1 bit per byte @@ -832,10 +858,11 @@ typedef volatile struct { [4] flex [5] dst ip6. */ u32 other_mask; - CLIB_PAD_FROM_TO (0xee78, 0xf000); + CLIB_PAD_FROM_TO (0xee78, 0xf000); } flow_director; - struct { + struct + { u32 l2_control[64]; u32 vlan_pool_filter[64]; u32 vlan_pool_filter_bitmap[128]; @@ -843,7 +870,7 @@ typedef volatile struct { u32 mirror_rule[4]; u32 mirror_rule_vlan[8]; u32 mirror_rule_pool[8]; - CLIB_PAD_FROM_TO (0xf650, 0x10010); + CLIB_PAD_FROM_TO (0xf650, 0x10010); } pf_bar; u32 eeprom_flash_control; @@ -852,26 +879,27 @@ typedef volatile struct { [15:2] address [31:16] read data. */ u32 eeprom_read; - CLIB_PAD_FROM_TO (0x10018, 0x1001c); + CLIB_PAD_FROM_TO (0x10018, 0x1001c); u32 flash_access; - CLIB_PAD_FROM_TO (0x10020, 0x10114); + CLIB_PAD_FROM_TO (0x10020, 0x10114); u32 flash_data; u32 flash_control; u32 flash_read_data; - CLIB_PAD_FROM_TO (0x10120, 0x1013c); + CLIB_PAD_FROM_TO (0x10120, 0x1013c); u32 flash_opcode; u32 software_semaphore; - CLIB_PAD_FROM_TO (0x10144, 0x10148); + CLIB_PAD_FROM_TO (0x10144, 0x10148); u32 firmware_semaphore; - CLIB_PAD_FROM_TO (0x1014c, 0x10160); + CLIB_PAD_FROM_TO (0x1014c, 0x10160); u32 software_firmware_sync; - CLIB_PAD_FROM_TO (0x10164, 0x10200); + CLIB_PAD_FROM_TO (0x10164, 0x10200); u32 general_rx_control; - CLIB_PAD_FROM_TO (0x10204, 0x11000); + CLIB_PAD_FROM_TO (0x10204, 0x11000); - struct { + struct + { u32 control; - CLIB_PAD_FROM_TO (0x11004, 0x11010); + CLIB_PAD_FROM_TO (0x11004, 0x11010); /* [3:0] enable counters [7:4] leaky bucket counter mode [29] reset @@ -884,56 +912,62 @@ typedef volatile struct { 0x10 reqs that reached timeout etc. */ u32 counter_event; - CLIB_PAD_FROM_TO (0x11018, 0x11020); + CLIB_PAD_FROM_TO (0x11018, 0x11020); u32 counters_clear_on_read[4]; u32 counter_config[4]; - struct { + struct + { u32 address; u32 data; } indirect_access; - CLIB_PAD_FROM_TO (0x11048, 0x11050); + CLIB_PAD_FROM_TO (0x11048, 0x11050); u32 extended_control; - CLIB_PAD_FROM_TO (0x11054, 0x11064); + CLIB_PAD_FROM_TO (0x11054, 0x11064); u32 mirrored_revision_id; - CLIB_PAD_FROM_TO (0x11068, 0x11070); + CLIB_PAD_FROM_TO (0x11068, 0x11070); u32 dca_requester_id_information; /* [0] global disable [4:1] mode: 0 => legacy, 1 => dca 1.0. */ u32 dca_control; - CLIB_PAD_FROM_TO (0x11078, 0x110b0); + CLIB_PAD_FROM_TO (0x11078, 0x110b0); /* [0] pci completion abort [1] unsupported i/o address [2] wrong byte enable [3] pci timeout */ u32 pcie_interrupt_status; - CLIB_PAD_FROM_TO (0x110b4, 0x110b8); + CLIB_PAD_FROM_TO (0x110b4, 0x110b8); u32 pcie_interrupt_enable; - CLIB_PAD_FROM_TO (0x110bc, 0x110c0); + CLIB_PAD_FROM_TO (0x110bc, 0x110c0); u32 msi_x_pba_clear[8]; - CLIB_PAD_FROM_TO (0x110e0, 0x12300); + CLIB_PAD_FROM_TO (0x110e0, 0x12300); } pcie; - u32 interrupt_throttle1[128-24]; - CLIB_PAD_FROM_TO (0x124a0, 0x14f00); + u32 interrupt_throttle1[128 - 24]; + CLIB_PAD_FROM_TO (0x124a0, 0x14f00); u32 core_analog_config; - CLIB_PAD_FROM_TO (0x14f04, 0x14f10); + CLIB_PAD_FROM_TO (0x14f04, 0x14f10); u32 core_common_config; - CLIB_PAD_FROM_TO (0x14f14, 0x15f14); + CLIB_PAD_FROM_TO (0x14f14, 0x15f14); u32 link_sec_software_firmware_interface; } ixge_regs_t; -typedef union { - struct { +typedef union +{ + struct + { /* Addresses bigendian. */ - union { - struct { + union + { + struct + { ip6_address_t src_address; u32 unused[1]; } ip6; - struct { + struct + { u32 unused[3]; ip4_address_t src_address, dst_address; } ip4; @@ -961,7 +995,7 @@ ixge_throttle_queue_interrupt (ixge_regs_t * r, u32 queue_interrupt_index, f64 inter_interrupt_interval_in_secs) { - volatile u32 * tr = + volatile u32 *tr = (queue_interrupt_index < ARRAY_LEN (r->interrupt.throttle0) ? &r->interrupt.throttle0[queue_interrupt_index] : &r->interrupt_throttle1[queue_interrupt_index]); @@ -1064,25 +1098,28 @@ ixge_throttle_queue_interrupt (ixge_regs_t * r, -typedef enum { +typedef enum +{ #define _(a,f) IXGE_COUNTER_##f, #define _64(a,f) _(a,f) foreach_ixge_counter #undef _ #undef _64 - IXGE_N_COUNTER, + IXGE_N_COUNTER, } ixge_counter_type_t; -typedef struct { +typedef struct +{ u32 mdio_address; /* 32 bit ID read from ID registers. */ u32 id; } ixge_phy_t; -typedef struct { +typedef struct +{ /* Cache aligned descriptors. */ - ixge_descriptor_t * descriptors; + ixge_descriptor_t *descriptors; /* Number of descriptors in table. */ u32 n_descriptors; @@ -1094,20 +1131,23 @@ typedef struct { u32 queue_index; /* Buffer indices corresponding to each active descriptor. */ - u32 * descriptor_buffer_indices; + u32 *descriptor_buffer_indices; - union { - struct { - u32 * volatile head_index_write_back; + union + { + struct + { + u32 *volatile head_index_write_back; u32 n_buffers_on_ring; } tx; - struct { + struct + { /* Buffer indices to use to replenish each descriptor. */ - u32 * replenish_buffer_indices; + u32 *replenish_buffer_indices; - vlib_node_runtime_t * node; + vlib_node_runtime_t *node; u32 next_index; u32 saved_start_of_packet_buffer_index; @@ -1152,15 +1192,17 @@ typedef struct { _ (82599_t3_lom, 0x151c) \ _ (x540t, 0x1528) -typedef enum { +typedef enum +{ #define _(f,n) IXGE_##f = n, foreach_ixge_pci_device_id #undef _ } ixge_pci_device_id_t; -typedef struct { +typedef struct +{ /* registers */ - ixge_regs_t * regs; + ixge_regs_t *regs; /* Specific next index when using dynamic redirection */ u32 per_interface_next_index; @@ -1179,7 +1221,7 @@ typedef struct { /* VLIB interface for this instance. */ u32 vlib_hw_if_index, vlib_sw_if_index; - ixge_dma_queue_t * dma_queues[VLIB_N_RX_TX]; + ixge_dma_queue_t *dma_queues[VLIB_N_RX_TX]; /* Phy index (0 or 1) and address on MDI bus. */ u32 phy_index; @@ -1195,11 +1237,12 @@ typedef struct { u64 counters[IXGE_N_COUNTER], counters_last_clear[IXGE_N_COUNTER]; } ixge_device_t; -typedef struct { - vlib_main_t * vlib_main; +typedef struct +{ + vlib_main_t *vlib_main; /* Vector of devices. */ - ixge_device_t * devices; + ixge_device_t *devices; /* Descriptor ring sizes. */ u32 n_descriptors[VLIB_N_RX_TX]; @@ -1218,9 +1261,9 @@ typedef struct { ixge_tx_descriptor_t tx_descriptor_template, tx_descriptor_template_mask; /* Vector of buffers for which TX is done and can be freed. */ - u32 * tx_buffers_pending_free; + u32 *tx_buffers_pending_free; - u32 * rx_buffers_to_add; + u32 *rx_buffers_to_add; f64 time_last_stats_update; } ixge_main_t; @@ -1228,7 +1271,8 @@ typedef struct { ixge_main_t ixge_main; vnet_device_class_t ixge_device_class; -typedef enum { +typedef enum +{ IXGE_RX_NEXT_IP4_INPUT, IXGE_RX_NEXT_IP6_INPUT, IXGE_RX_NEXT_ETHERNET_INPUT, @@ -1239,3 +1283,11 @@ typedef enum { void ixge_set_next_node (ixge_rx_next_t, char *); #endif /* included_ixge_h */ + +/* + * fd.io coding-style-patch-verification: ON + * + * Local Variables: + * eval: (c-set-style "gnu") + * End: + */ |