Age | Commit message (Collapse) | Author | Files | Lines |
|
From GCC 12, march=armv9-a option is supported, which includes the sve
and crc options needed. Furthermore, VPP L3Fwd benchmark results on N2
based servers show that N_PREFETCH set to 6 gives the best performance.
Type: feature
Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com>
Signed-off-by: Jieqiang Wang <jieqiang.wang@arm.com>
Change-Id: I9c4fcad84d4db1189d956dabab22b26d020fbfd6
|
|
Type: improvement
Change-Id: Ief77ae7338667ede290aece6933bb5ae2e76ffc6
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Type: improvement
Change-Id: I98eeba1ad2f9ed0531a7c615e0e70e535f24f813
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Type: feature
- Added multiarch support for AMD Zen architectures
Change-Id: I65d3fe94b6cc622ebecbe1ac803efa674e87c87a
Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
|
|
for testing purposes, disabled by default
Type: improvement
Signed-off-by: Damjan Marion <damarion@cisco.com>
Change-Id: Id616e2b3b21ae0f0b44e2b55ecefd501afacc7f2
|
|
Disabled by default..
Type: improvement
Change-Id: I36176c009e0873c048874ae38a7ea0a91449235c
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Significantly reduces compilation time for uses who are interested
to run binaries only on the build machine.
Type: make
Change-Id: I431f6f7374b6dfa8b3f7c72dc69f3d5cafd1f6bb
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Type: improvement
Change-Id: Ic07010f11ef303f5213a33b0faf24aaedb62f110
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Type: make
Change-Id: I51f30edb91e09525ba116fe3941f2e43f9718da7
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Type: make
Change-Id: I37fb925a9cc2dfc21dd7874f4b20a6943b28efc8
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Type: make
Change-Id: I53f7995c7e7a7ff829c662d71f37d88780bdd140
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Fix dependency issues where multi-arch file is using API generated file.
Type: improvement
Change-Id: I5d4af7a630529bc138c35841723e38938f36d963
Signed-off-by: Ole Troan <ot@cisco.com>
|
|
Performance improvement: on supported platforms, currently only Intel Tremont,
use a write combining store to update the tail pointers.
Also, Tremont node variant is added for all.
Type: improvement
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Change-Id: Ie9606e403b7d9655184f778e3ffee3027c8c9edd
|
|
Without this, if a multiarch source depends on a generated api header
for instance, the build would be racy between the api header generation
and the multiarch object compilation.
Type: improvement
Signed-off-by: Aloys Augustin <aloaugus@cisco.com>
Change-Id: I08fcd0e5a1c51398ac1a8f37cf6562064b400d4a
|
|
Type: feature
- Added multiarch support for Marvell OCTEONTX2
- Corrected Marvell THUNDERX2 spelling
Signed-off-by: Nitin Saxena <nsaxena@marvell.com>
Change-Id: I42d3654aeda89759a2db9d695592ee3227b26c2b
|
|
Type: improvement
Change-Id: Ief243f88e654e578ef9b8060fcf535b364aececb
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Enable arch-specific compiling and dynamic optimal function selection
for Arm Neoverse-N1.
Support for -march=armv8.2-a+crc+crypto -mtune=neoverse-n1 for
Neoverse-N1 is added starting from gcc-9.2.0
without change with change improvement
[L2 - 1x flows] 11.00 Mpps 11.46 Mpps 4%
[L2 - 10Kx flows] 6.83 Mpps 7.17 Mpps 5%
[L3 - 1x flows] 10.39 Mpps 10.78 Mpps 3.7%
[L3 - 10Kx flows] 6.67 Mpps 7.19 Mpps 7.8%
Type: feature
Change-Id: I5d24d17820b3dd6909b913202e8c31fc7d48650f
Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com>
Reviewed-by: Jieqiang Wang <Jieqiang.Wang@arm.com>
Reviewed-by: Govindarajan Mohandoss <Govindarajan.Mohandoss@arm.com>
|
|
Type: fix
Change-Id: I098f6c79be3c2e4db001edc0cf0a229bf6e0b13d
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Type: feature
Change-Id: Ic8aa6c48913677537301971469f9627b70c1cec8
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
VERSION_GREATER_EQUAL is not supported before CMake version 3.7.
Type: fix
Signed-off-by: Jianlin Lv <Jianlin.Lv@arm.com>
Change-Id: Id690b7b7c26121f9d289ebd0aaea0860be63795f
|
|
fix compile issue that caused by enabling "-mtune=thunderx2t99"
flag during compilation, such as
"/opt/vpp-agent/dev/vpp/src/vnet/interface_stats.c:164:1:
internal compiler error: Segmentation fault"
Type: fix
Change-Id: Iaf9f80a6c203a7e5b6a40523f14a62bb37091c92
Signed-off-by: Jianlin Lv <Jianlin.Lv@arm.com>
|
|
Type: refactor
Change-Id: I8489ccd54411c2aa9355439c5641dc31012c64a2
Signed-off-by: Benoît Ganne <bganne@cisco.com>
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
The current aarch64 version of VPP package distro in cloud repository
(https://packagecloud.io/fdio/master/ubuntu), is built on a ThunderX server,
using some arch-specific options, for example, 128Byte cache line size,
T=arm64-thunderx-linuxapp-gcc, RTE_MACHINE=thunderx
The patch is trying to build package distro with aarch64 generic features,
for both binary type targets, e.g., build/build-release, and package type
targets, e.g., pkg-deb/pkg-rpm, with the generic options, e.g.,
128Byte cache line size, T=arm64-armv8a-linuxapp-gcc, RTE_MACHINE=armv8a
If end users want to build arch specific optimized image,
TARGET_PLATFORM variable could be used, as below example,
$ make build-release/pkg-deb TARGET_PLATFORM=thunderx
Change-Id: If78bca8709fe83db6a95e8c26346f206bf5ea71d
Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com>
Reviewed-by: Sirshak Das <Sirshak.Das@arm.com>
Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
|
|
-fno-common makes sure we do not have multiple declarations of the same
global symbol across compilation units. It helps debug nasty linkage
bugs by guaranteeing that all reference to a global symbol use the same
underlying object.
It also helps avoiding benign mistakes such as declaring enum as global
objects instead of types in headers (hence the minor fixes scattered
across the source).
Change-Id: I55c16406dc54ff8a6860238b90ca990fa6b179f1
Signed-off-by: Benoît Ganne <bganne@cisco.com>
|
|
Change-Id: Ib9c2aba1eda08a22465441e33553b9b744c79d56
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Currently, there are three variants available on aarch64, qdf24xx, thunderx2t99, and cortex-a72.
-DCLIB_N_PREFETCHES is passed to source code to select dual/quad implementation.
Besides, different compiler options are applied on these critical functions.
gcc-7.3.0 reports ICE(internal compiler error) with -mtune=thunderx2t99,
so -mtune=thunderx2t99 is enabled only when gcc version is greater than 7.3.0
Cavium ThunderX2, Impermenter 0x43, Part 0x0af
-march=armv8-a+crc+crypto -mtune=thunderx2t99
Qualcomm Centriq 2400, Impermenter 0x51, Part 0xc00
-march=armv8.1-a+crc+crypto -mtune=qdf24xx
Cortex-A72, Impermenter 0x41, Part 0xd08
-march=armv8-a+crc+crypto -mtune=cortex-a72
Change-Id: Id5649c6325c1e642d0fd42535e3908793b13e02a
Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com>
Reviewed-by: Sirshak Das <sirshak.das@arm.com>
Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
|
|
It is packaging responsibility to put libs in the right place.
Use of lib64 resulted in huge amount of files with hardcoded lib64.
This patch simplifies things...
Change-Id: Iab0dea0583e480907732c5d2379eb951a00fa9e6
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
According to Nitin Saxena ThunderX2 machine has 64B cache line whilst
all others are 128B. According to Damjan, Nitin's previous patch broke
compilation for all non-Cavium machines. This patch should make
everything happy again.
Change-Id: I8c5c2661f9f2f9c3e9b0965a277712f9a1eefa5f
Signed-off-by: Marco Varlese <marco.varlese@suse.com>
|
|
Change-Id: I7b7183b4603076e5afac096545d820091ee7c495
Signed-off-by: Nitin Saxena <nitin.saxena@cavium.com>
|
|
Change-Id: I9a0df8d15deefdf31cfead56c96433cd7220b802
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Change-Id: If5b850c939f7a5383f9a7eff8ac41708c3428a90
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
While not sure if this is right or not, this is what autotools do
Change-Id: I01f22281302b1383b0e69c3f03e5c8f8a8961358
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Change-Id: Ibcb7105fa7e3c09efdce01bccd4de235fe33ea99
Signed-off-by: Damjan Marion <damarion@cisco.com>
|