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vpclmulqdq is introduced on intel icelake architecture and
allows computing 4 carry-less multiplications in paralled by using
512-bit SIMD registers
Type: feature
Change-Id: Idb09d6f51ba6f116bba11649b2d99f649356d449
Signed-off-by: Damjan Marion <damjan.marion@gmail.com>
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This allows us to combine 2 XOR operations into signle instruction
which makes difference in crypto op:
- in x86, by using ternary logic instruction
- on ARM, by using EOR3 instruction (available with sha3 feature)
Type: refactor
Change-Id: Ibdf9001840399d2f838d491ca81b57cbd8430433
Signed-off-by: Damjan Marion <damjan.marion@gmail.com>
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Type: improvement
Change-Id: I1f204685ea9374389fc24fc53184ce06806beed3
Signed-off-by: Damjan Marion <dmarion@me.com>
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Type: refactor
Change-Id: I1d594af6d7c0d065d5c2decc5b22d549189b1882
Signed-off-by: Damjan Marion <dmarion@me.com>
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Type: refactor
Change-Id: I76733a9ed362ec60badd22c0fbc2a9c5749da88d
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: refactor
Change-Id: I9f21b3bf669ff913ff50afe5459cf52ff987e701
Signed-off-by: Damjan Marion <damarion@cisco.com>
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