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Change-Id: I90600d000afb02e8969f3c01bcf9e4b5c10a7d39
Signed-off-by: Mohsin Kazmi <sykazmi@cisco.com>
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Change-Id: Ib61f0299c17c0f021408ab0a44c5b54f55f8a8ec
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: Iffd5c45ab242a919592a1f686f7f880936b68a1a
Signed-off-by: Damjan Marion <damarion@cisco.com>
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This adds a `num-mem-channels` option for DPDK enabling support for
choosing the number of memory channels used.
Change-Id: I1663dd866ac60592b6dd02261af66d87c64acdb1
Signed-off-by: Jessica Tallon <tsyesika@igalia.com>
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Change-Id: Id4b73368382b5e78c138987fe092429af5cb0afd
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: I53cad8e7787a132a5d6bacd5fda3fe67b7d59b44
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: Ibc59323e849810531dd0963e85493efad3b86857
Signed-off-by: Damjan Marion <damarion@cisco.com>
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DPDK 18.08 verifies if all set bits are supported and fails if not....
Change-Id: Ia87242fcda11147dff3bebe2e2bef32f0a8891fb
Signed-off-by: Damjan Marion <damarion@cisco.com>
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This significantly reduces need for
...
in multiarch code. Simply constructor macros will jost create static unused
entry if CLIB_MARCH_VARIANT is defined and that will be optimized out by
compiler.
Change-Id: I17d1c4ac0c903adcfadaa4a07de1b854c7ab14ac
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: If1b93341c222160b9a08f127620c024620e55c37
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: I39f87ca161c891fb22462a23188982fef7c3243f
Signed-off-by: Mohsin Kazmi <sykazmi@cisco.com>
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dpdk raw item match string changed from flexible array member to a
pointer member
Change-Id: I930f05112ce04b0cdb3feb985d755e730b102084
Signed-off-by: Eyal Bari <ebari@cisco.com>
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Needed a spinlock to protect the data vector. Cleaned up debug cli so
the output makes sense, and so that various parameters exist in one
place. Removed a nonsense memset-to-zero which led to ultra-confusing
results.
Change-Id: I91cd14ce7fe84fd2eceab86e016b5ee001993be4
Signed-off-by: Dave Barach <dbarach@cisco.com>
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Change-Id: I63c36644c9d93f2c3ec6606ca0205b407499de4e
Signed-off-by: Eyal Bari <ebari@cisco.com>
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Fix a typo from previous patch. Change 0x104 to 0x1004.
Change-Id: I82230a8a0ec01567eb1d4bc12ac02062c2a98347
Signed-off-by: Matthew Smith <mgsmith@netgate.com>
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If a PMD writes too many log messages using rte_vlog(), the
pipe for logging can fill and then rte_vlog() will block
on fflush() while it waits for something to read from the other
side of the pipe. That will never happen since the process node
that would read the other side of the pipe runs in the
same thread.
Set the write fd to non-blocking before the call to
rte_openlog_stream(). If the pipe is full, calls to write() or
fflush() will fail but execution will continue.
Change-Id: I0e5d710629633acda5617ff29897d6582c255d57
Signed-off-by: Matthew Smith <mgsmith@netgate.com>
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Recognize the PF and VF device IDs for the Mellanox adapter
used on Azure.
Change-Id: Ic7b36b37ac93db2b696354ffe6fa2b6d62ee3801
Signed-off-by: Matthew Smith <mgsmith@netgate.com>
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This patch addresses the coverity scan warnings reported for the DPDK
plugin.
Change-Id: Ie7ac7ffcf4a6c63245eae0f9910a193ab1e318a8
Signed-off-by: Marco Varlese <marco.varlese@suse.de>
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Configure w/ --enable-dlmalloc, see .../build-data/platforms/vpp.mk
src/vppinfra/dlmalloc.[ch] are slightly modified versions of the
well-known Doug Lea malloc. Main advantage: dlmalloc mspaces have no
inherent size limit.
Change-Id: I19b3f43f3c65bcfb82c1a265a97922d01912446e
Signed-off-by: Dave Barach <dave@barachs.net>
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The driver implements Cavium QLogic FastLinQ QL4xxxx 10G/25G/40G/50G/100G
Intelligent Ethernet Adapters (IEA) and Converged Network Adapters (CNA)
(doc/guides/nics/qede.rst)
Change-Id: If17e8cb572eb8c0585085be1c7cfdfa159eb6e68
Signed-off-by: Igor Mikhailov (imichail) <imichail@cisco.com>
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Change-Id: If4da80c7eefe55905594eaaba0946d75f0892da5
Signed-off-by: Igor Mikhailov (imichail) <imichail@cisco.com>
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Change-Id: I6fa4c6bf9c4e96ba4502a06907bdecc654ace665
Signed-off-by: Damjan Marion <damarion@cisco.com>
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- Some crypto devices rely on rte_cryptodev_start() API to be called by
application to enable a pre-configured H/W Crypto device.
- NXP dpaa2 is one of the example.
Change-Id: I2ad8ca0060604fb4e0541161e91bdebc6642f4da
Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com>
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Change-Id: I7c611d3fa7fabe82294fc22a61d5a3927a2da39d
Signed-off-by: Jessica Tallon <tsyesika@igalia.com>
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Workaround for lack of driver interrupt support. Also quite handy for
home gateway, laptop/vagrant, other use-cases not requiring maximum
vectors/second for proper operation.
Change-Id: Ifc4b98112450664beef67b89ab8a6940a3bf24b5
Signed-off-by: Dave Barach <dave@barachs.net>
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Change-Id: I23caebf602e3e6ff45fdec106a0da88f6de7a284
Signed-off-by: Igor Mikhailov (imichail) <imichail@cisco.com>
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Change-Id: I024c1d398fcb51e5a20f9049d16a87b3b1ba0c20
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
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Change-Id: I737dad64bf6dd0743d36500d5cfa1cb1a6594b98
Signed-off-by: Eyal Bari <ebari@cisco.com>
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ip4 vxlan cli/api (using flow infra) to create flows and enable them on
different hardware (currently tested with i40e)
to offload a vxlan tunnel onto hw:
set flow-offload vxlan hw TwentyFiveGigabitEthernet3/0/0 rx vxlan_tunnel1
to remove offload:
set flow-offload vxlan hw TwentyFiveGigabitEthernet3/0/0 rx vxlan_tunnel1 del
TODO:ipv6 handling
Change-Id: I70e61f792ef8e3f007d03d7df70e97ea4725b101
Signed-off-by: Eyal Bari <ebari@cisco.com>
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Change-Id: Iee8de25ab3c68ae3698c79852195dc336050914c
Signed-off-by: Ole Troan <ot@cisco.com>
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This patch separates setting of hardware interfaec and software
interface MTU. Software MTU is L2 payload MTU (i.e. not including L2
header). Per-protocol MTU for IPv4, IPv6 and MPLS can also be set.
Currently only IP4, IP6 are enabled in adjacency / rewrite code.
Documentation in src/vnet/MTU.md
Change-Id: Iee2fd6f0bbc8210748dd8e073ab9fab87d323690
Signed-off-by: Ole Troan <ot@cisco.com>
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... introduced with dpdk 18.05 support patch
Change-Id: Idf2283888f81d7652599651c0d65476e451f9343
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Added code to initialize failsafe PMD
This is part of initial effort to enable vpp running over
dpdk on failsafe PMD in Microsoft Azure(4/4).
Change-Id: Ia2469c7087ca4b5c7881dfb11ec5c4fcebaa1d04
Signed-off-by: Rui Cai <rucai@microsoft.com>
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Change-Id: I205932bc727c990011bbbe1dc6c0cf5349d19806
Signed-off-by: Damjan Marion <damarion@cisco.com>
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- Modify the API send_ip6_na and send_ip4_garp to take sw_if_index instead
of vnet_hw_interface_t and add call to build_ethernet_rewrite to support
subinterface/vlan
- Add code to bonding driver to send an event to bond_process when the first
interface becomes active or when the active interface is down
- Create a bond_process to walk the interface and the corresponding
subinterfaces to send garp/ip6_na when an event is received.
- Minor cleanup in bonding/node.c
Note: dpdk bonding driver does not send garp/ip6_na for subinterfaces. There is
no attempt to fix it here. But the infra is now done and should be easy to
add the support.
Change-Id: If3ecc4cd0fb3051330f7fa11ca0dab3e18557ce1
Signed-off-by: Steven <sluong@cisco.com>
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Added configure argument "--with-log2-cache-line-bytes=5|6|7|auto"
AKA 32, 64, or 128 bytes, or use the inferred value from the build host.
produces build-xxx/vpp/vppinfra/config.h, which .../src/vppinfra/cache.h
Kernels which implement the following pseudo-file (aka x86_64) are
easy: /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size
Otherwise, extract the cpuid from /proc/cpuinfo and map it to the
cache line size.
Change-Id: I7ff861e042faf82c3901fa1db98864fbdea95b74
Signed-off-by: Dave Barach <dave@barachs.net>
Signed-off-by: Nitin Saxena <nitin.saxena@cavium.com>
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~5 clocks/packet improvement...
Change-Id: I1a78fa24dcd1b3ab7f45e10b9ded50f79517114a
Signed-off-by: Damjan Marion <damarion@cisco.com>
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This is ~50% improvement in buffer alloc performance.
For a 256 buffer allocation, it was ~10 clocks/buffer, now is < 5 clocks.
Change-Id: I97590e240a79a42bcab5eb26587fc2d11e6eb163
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Prior to the change, dpdk plugin assumes xd->device_index is
used both as index for internal dpdk_main->devices array
and DPDK port index to call into DPDK APIs.
However, when running on top of Failsafe PMDs,
DPDK port index range may no longer be contiguous (as noted:
http://dpdk.org/ml/archives/dev/2018-March/092375.html
for related changes in DPDK). Because this, dpdk plugin can
no longer iterate through all available DPDK ports
with a for 0->rte_eth_dev_count() loop and the assumption of
device_index no longer holds.
This is part of initial effort to enable vpp running over
dpdk on failsafe PMD in Microsoft Azure(3/4).
Change-Id: I416fd80f2d40e12e139f8f3492814da98343eae7
Signed-off-by: Rui Cai <rucai@microsoft.com>
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This fixes some compilation warnings with clang on AArch64.
Change-Id: Idb941944e3f199f483c80e143a9e5163a031c4aa
Signed-off-by: Damjan Marion <damarion@cisco.com>
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port_id be used for dpdk port_id
Change-Id: Ia7d8cdc5dec2ad658c11f9c0f3ef8005a470ac3c
Signed-off-by: Damjan Marion <damarion@cisco.com>
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This breaks VFIO operation.
This reverts commit d3b3baa4f8e9e4d95264aff16fe85434ef8061bd.
Change-Id: I2482e0da2d1ebfc365d13668c4b992b040f561b4
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: Ibab5e27277f618ceb2d543b9d6a1a5f191e7d1db
Signed-off-by: Damjan Marion <damarion@cisco.com>
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1、Adding PMD type for support Cavium LiquidIO II CN23XX NIC;
2、Our company is using VPP + DPDK +Cavium LiquidIO II CN23XX NIC,
Unfortunately, the latest VPP code does not support
Cavium LiquidIO II CN23XX pci.
So I increased the PMD type to support LiquidIO NIC,
and can run normally, we most subsequent projects are
based on VPP + DPDK + Cavium LiquidIO II CN23XX NIC model,
so I hope VPP team can adopt this requirement, thanks a lot.
Change-Id: I604ae444d69b37c2e26962bfe4ccdfe983b75041
Signed-off-by: chuhong yao <ych@panath.cn>
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- Currently mempool priv size is getting initialized after releasing buffers
to pool. This is causing mismatch in expected & real metadata size value
and buffers are getting released with wrong offset. (when metadata offset
is in use for a given platform)
- Since private data size is 0 initially, metadata size don't include space
for VLIB_BUFFER_HDR.
Change-Id: I780c4d518104631a3dcf192185bacf58b3598e65
Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com>
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- Fix the issue where eal iova mode is Virtual Address (RTE_IOVA_VA) but
setting DMA iova address to Physical address value always.
Change-Id: Ib1e9c1596d95885c7eff11723338121627203e61
Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com>
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The option no-multi-seg doesn't take effect for RX since MTU
which is too large is passed to DPDK lib, Which causes PMDs
are running XXX_scattered_rx function. The patch fixes the issue.
Change-Id: I91a6fb23fd118e872c8a52a6c35c36a86cb2c02b
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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Should cost at most 1 clock per frame when not enabled.
Add "pcap rx trace..." debug CLI, refactored "pcap tx trace" debug CLI
to avoid duplicating code.
Change-Id: I19ac75d1cf94a6a24c98facbf0753381d37963ea
Signed-off-by: Dave Barach <dbarach@cisco.com>
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Change-Id: Ic9f98c022e32715af395c9ed618589434eb0e526
Signed-off-by: Eyal Bari <ebari@cisco.com>
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Replace hash with a vector to improve performance.
Plus other minor performance improvements.
Change-Id: I3f0ebd909782ce3727f6360ce5ff5ddd131f8574
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
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