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Type: fix
Change-Id: Ifb2e4d93dcf8648b1bd66f4c0ee937295683bd87
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Originally cryptodev doesn't support chacha20-poly1305 with aad length
0.
This patch add support in cryptodev for chacha20-poly1305 with aad
length 0. This length is using in Wireguard.
Type: improvement
Signed-off-by: Gabriel Oginski <gabrielx.oginski@intel.com>
Change-Id: I0608920bb557d7d071e7f9f37c80cf50bad81dcc
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Type: fix
Change-Id: Ic5b74fb7a8e479e8cdccbb6a564ff3fdd299455c
Signed-off-by: Benoît Ganne <bganne@cisco.com>
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Also improve logging....
Type: fix
Change-Id: I3d3aee52cd45e59ecd6ce13bd516c66559638fec
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Change-Id: I3659de6599f402c92e3855e3bf0e5e3388f2bea0
Signed-off-by: Damjan Marion <damarion@cisco.com>
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- per hw-interface-class handlers
- ethernet set_mtu callback
- driver can now refuse MTU change
Type: improvement
Change-Id: I3d37c9129930ebec7bb70caf4263025413873048
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Change-Id: I9772088bca176fd0fdb162677ec55c59aa8f3adf
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: fix
Fixes: 65105c95f
Change-Id: I8dee4b560a49891f954d7eb8e79ea535cedeaa88
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: feature
This patch bumps dpdk version from 21.08 to 21.11
Change-Id: Id37fdba75f1ea4f4eac3c92226f3b1c539e1daca
Signed-off-by: Dastin Wilski <dastin.wilski@gmail.com>
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Change-Id: If61d7409ff14b9f771c1dc8ec9f35e179cea7a28
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Change-Id: Ib2c55dd2a246a690b2089f5c0b88508f732281f2
Signed-off-by: Damjan Marion <damarion@cisco.com>
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This prevents crash due to worker tread accessing device data
while device vector is growing.
Type: fix
Change-Id: I5cf9f53ddbe97fe52db8fd431ea7c0e480f3d4bc
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Change-Id: I2cd37f0c1a1ed33438bfa4b7590e5609e5094fc8
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Also change the way how we dig function pointer so it works with dpdk
21.11+
Type: improvement
Change-Id: I38d5909eea9c2893651710bd45057b1635aa7b37
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: fix
Change-Id: I7aa172e58c970c4971db6ef2ff5b199b7f3c0b99
Signed-off-by: Dastin Wilski <dastin.wilski@gmail.com>
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Type: improvement
Change-Id: Ibf43aa483548e6055e4b851ad893371d7af3b018
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Change-Id: If5636d4376fb06da62f947c28b18c07b6ad21722
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Change-Id: I4ead18dee249a27b4dbb8bbf53b6238d91042890
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Change-Id: I9022e29ebc0edb7946d374d6c3c45ee6962d725f
Signed-off-by: Damjan Marion <damarion@cisco.com>
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introduced in DPDK 21.11
Type: improvement
Change-Id: I8c845949dd904a2bf8fa4a91e2f3ae5d704f2283
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Prep for supporting multiple callbacks, optional args, etc.
Type: improvement
Change-Id: I96244c098712e8213374678623f12527b0e7f387
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: fix
Signed-off-by: Florin Coras <fcoras@cisco.com>
Change-Id: I48ac0a2c77154b5232a0fe4166518f28d1f1d8ef
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Type: improvement
Change-Id: I4b929693f3671be8ee63a58afcbac75a27d99d57
Signed-off-by: Damjan Marion <damarion@cisco.com>
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enic driver now properly exposes speed_capa bitmap so this workaround
is not needed anymore.
Type: refactor
Change-Id: Ic754de0b9de32d488405ffcd8d62dd6aa035d2bc
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: refactor
Change-Id: I41d5d07eef670e89eba8fd816e123981940b5d79
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Change-Id: Ifd5201c101da7f4fb63f9b64280a6ec35b2af6a0
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Based on gerrit 26480 by chenmin.sun@intel.com
Signed-off-by: Florin Coras <fcoras@cisco.com>
Change-Id: Id8f2127f0fac5f555b38483714fe92c038875915
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Make it shorter to type, easier to debug, make adding callbacks in
future simpler.
Type: improvement
Change-Id: I6cdd6375e36da23bd452a7c7273ff42789e94433
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: refactor
Change-Id: I0bce385c7e391fa2b74646d001980610f80f7062
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: refactor
Change-Id: Iff96a79323d7d428a779e9736e07c1dc9dddb518
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Change-Id: Idb0b079df49c12643c9a93ee0effe011d3489068
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: refactor
Change-Id: I2de762953faa5056d5fefa678e4faafbe7710dc6
Signed-off-by: Damjan Marion <damarion@cisco.com>
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This code was actually never working. It was just used as workaround for
Cisco ENIC issue with tagged default vlan frames.
Today Cisco ENIC provides solution to this problem with devargs flags...
Change-Id: Ia8284274117cb200bf6c7f7911d945d5a093d878
Type: refactor
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Type: improvement
Previously multiple sw crypto scheduler queues per core design
caused unaverage frame processing rate for each async op ID –
the lower the op ID is the highly likely they are processed first.
For example, when a RX core is feeding both encryption and
decryption jobs of the same crypto algorithm to the queues at a
high rate, in the mean time the crypto cores have no enough
cycles to process all: the jobs in the decryption queue are less
likely being processed, causing packet drop.
To improve the situation this patch makes every core only owning
a two queues, one for encrypt operations and one for decrypt.
The queue is changed either after checking each core
or after founding a frame to process.
All crypto jobs with different algorithm are pushed to
thoses queues and are treated evenly.
In addition, the crypto async infra now uses unified dequeue handler,
one per engine. Only the active engine will be registered its
dequeue handler in crypto main.
Signed-off-by: DariuszX Kazimierski <dariuszx.kazimierski@intel.com>
Signed-off-by: PiotrX Kleski <piotrx.kleski@intel.com>
Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
Signed-off-by: Jakub Wysocki <jakubx.wysocki@intel.com>
Change-Id: I517ee8e31633980de5e0dd4b05e1d5db5dea760e
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It is actually longer and slower...
Type: refactor
Change-Id: I0f126d4cdb13ecc60a2d370409f23820d7f7eb72
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Now DPDK have API to register external threads so we can remove this
mess...
Type: improvement
Change-Id: I71a21f0cd94bd668aa406710c75a0bcc63fdc840
Signed-off-by: Damjan Marion <damarion@cisco.com>
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TCP csum offload fails although udp seems to work.
Type: fix
Fixes: fa1fb60
Signed-off-by: Florin Coras <fcoras@cisco.com>
Change-Id: Ie0651887b09920365806eaad776b0d13059faee8
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Type: improvement
This patch adds AES-CTR-128/192/256 + SHA1 linked algo support to dpdk
cryptodev.
Signed-off-by: PiotrX Kleski <piotrx.kleski@intel.com>
Change-Id: Idc162b29f4075ef8be9577abd3daf6de05f84faa
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Originally cryptodev allocates mempools for seesion and session private
data during its initialization. Moreover the size of these mempools are
fixed resulting in limited session count (up to value specified in
CRYPTODEV_NB_SESSION macro).
This patch allows for session count to scale up by allocating new
mempools as they are needed during session creation.
Type: improvement
Signed-off-by: Dastin Wilski <dastin.wilski@gmail.com>
Change-Id: I6ae240b474d3089d3ff50ca5bc7ff48f149983db
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Changed dpdk-input prefetch of vlib_buffer_t to prefetchw.
vlib_buffer_t was being prefetched without 'ownership', which may
cause a stall when the buffer is subsequently written to. This saves
4 clocks a packet when the buffer is shared a cross cores, and has no
impact when not sharing.
Type: improvement
Signed-off-by: Ray Kinsella <mdr@ashroe.eu>
Change-Id: I317af2a38ef536022e68552351a8507861f62dad
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Type: improvement
Signed-off-by: Florin Coras <fcoras@cisco.com>
Change-Id: Ia25e671084dd2c0010c0577649bf51ba6495b6ac
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Add a hint so that it's obvious that fall through in switch statement is
intentional.
Type: fix
Fixes: 34c54dff5c
Signed-off-by: Klement Sekera <ksekera@cisco.com>
Change-Id: I12271227424761fb89b03a390f626c2ab466472c
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Type: refactor
Change-Id: I76ccf8970ebb3f180ce745d8b515c5e0724784d6
Signed-off-by: Damjan Marion <damarion@cisco.com>
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- move existing ethernet hash functions to hash infra (no l4
awareness)
- refactor code to use hash infra and add apis to request l4 aware
hashing functions
- hashing functions per interface
- code cleanup
Type: improvement
Signed-off-by: Florin Coras <fcoras@cisco.com>
Change-Id: Ia9f44db98d83f0f027aeb37718585a2e10ffd2c6
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unformat_init_vector() expects a vector, not a NULL-terminated C-string.
Type: fix
Change-Id: I20a266243f63d94b0c6fe24e25ee8346c08c8ff2
Signed-off-by: Benoît Ganne <bganne@cisco.com>
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Type: improvement
Change-Id: Ic7c2ac4237ecd192def7c3530ae5f788c62cf9ad
Signed-off-by: Benoît Ganne <bganne@cisco.com>
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Type: fix
Signed-off-by: Florin Coras <fcoras@cisco.com>
Change-Id: I89fb738903ee74ffcb7c77a041391f0388df6991
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Type: improvement
Signed-off-by: Mohsin Kazmi <sykazmi@cisco.com>
Change-Id: I10141033030342881298d70742fa5bdea402b4c9
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CLIB_PREFETCH (cop[1], CLIB_CACHE_LINE_BYTES * 3, STORE);
Note on 64 bytes cache line size arm machines,
CLIB_CACHE_LINE_BYTES 128
CLIB_CACHE_PREFETCH_BYTES 6
above CLIB_PREFETCH () macro will be expand to
ASSERT ((size) <= 4 * CLIB_CACHE_PREFETCH_BYTES);
it will hit assert due to size (i.e. 3 * 128) > 4 * 64
Solution:
Change to CLIB_PREFETCH (cop[1], sizeof(*cop[1]), STORE);
Type: fix
Signed-off-by: Tianyu Li <tianyu.li@arm.com>
Reviewed-by: Lijian Zhang <lijian.zhang@arm.com>
Change-Id: Id0981fd5bd2b25ff71db4197b25578d0b7a9803e
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Coverity does not seem happy about exotic control
flows in switch/case statements
Change-Id: Ie006190058f811aacf85125ebc58330d9c53510f
Signed-off-by: Mohammed Hawari <mohammed@hawari.fr>
Type: fix
Fixes: 0b42ac565b970c186a9ad734f980b440f56fb25b
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