Age | Commit message (Collapse) | Author | Files | Lines |
|
Current loadbalancer seems to rewrite the 17th and 18th octet of L4 header regardless of which kind of L4 protocol is used in case of L3DSR.
In case UDP, it rewrites 9th and 10th octet of payload (because UDP header is 8 octets long). If UDP payload is less than 8 octets, UDP checksum becomes invalid.
In other protocols similar problems is likely to occue.
This patch checks which L4 protocol is used, and rewrite packet regarding the L4 protocol.
Signed-off-by: Hiroki Narukawa <nhirokinet@nhiroki.net>
Change-Id: I84390ff58a33f05efac0421856beea89014adc72
Type: fix
|
|
Type: fix
Signed-off-by: Dave Barach <dave@barachs.net>
Change-Id: Ibad744788e200ce012ad88ff59c2c34920742454
|
|
- When deleting VIP member with flush, VPP will crash.
- When deleting VIP member without flush, vpp won't crash.
- This crash is almost 100% reproductive.
Ticket: VPP-1680
Type: fix
Change-Id: Ia4e8f9e0f987176c7f6ec52c92e66563f313b0c3
Signed-off-by: Hongjun Ni <hongjun.ni@intel.com>
|
|
Change-Id: Ic6823fb617ecae547a5f0e28b1e037848e40f682
Signed-off-by: Dave Barach <dave@barachs.net>
|
|
Previously, a service is specified by vip.
This patch extend that a service is specified
by both vip and per-port-vip cases.
Change-Id: Icbfd1f972c6bafde7d85c6abb498576bd9ba250d
Signed-off-by: Hongjun Ni <hongjun.ni@intel.com>
|
|
It is cheaper to get thread index from vlib_main_t if available...
Change-Id: I4582e160d06d9d7fccdc54271912f0635da79b50
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Change-Id: Iedebbac71d3e694b915d6a126c80ecc3b5473a4a
Signed-off-by: Hongjun Ni <hongjun.ni@intel.com>
|
|
Add support of NAT66
Change-Id: Ie6aa79078a3835f989829b9a597c448dfd2f9ea3
Signed-off-by: Hongjun Ni <hongjun.ni@intel.com>
|
|
Though dst-IP address would be change in LB plugin with L3DSR method,
layer-4 checksum would not be recomputed after this change.
Related changes:
- L3DSR: https://gerrit.fd.io/r/#/c/10203/
Change-Id: I98de7b8d80186ac77608a68050208c08d90b7c3b
Signed-off-by: Yusuke Tatsumi <ytatsumi@yahoo-corp.jp>
|
|
L3DSR is used to overcome Layer 2 limitations
of Direct Server Return Load Balancing.
It maps VIP to DSCP bits, and reuse TOS bits to transfer it
to server, and then server will get VIP from DSCP-to-VIP mapping.
Please refer to https://www.nanog.org/meetings/nanog51/presentations/Monday/NANOG51.Talk45.nanog51-Schaumann.pdf
Change-Id: I403ffeadfb04ed0265086eb2dc41f2e17f8f34cb
Signed-off-by: Hongjun Ni <hongjun.ni@intel.com>
|
|
Change-Id: Ic1c440b2594c3ec4cdc75730069f16432cdb9587
Signed-off-by: Hongjun Ni <hongjun.ni@intel.com>
|
|
This patch deprecates stack-based thread identification,
Also removes requirement that thread stacks are adjacent.
Finally, possibly annoying for some folks, it renames
all occurences of cpu_index and cpu_number with thread
index. Using word "cpu" is misleading here as thread can
be migrated ti different CPU, and also it is not related
to linux cpu index.
Change-Id: I68cdaf661e701d2336fc953dcb9978d10a70f7c1
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Change-Id: I1c3b87e886603678368428ae56a6bd3327cbc90d
Signed-off-by: Damjan Marion <damarion@cisco.com>
|