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2021-08-20rdma: decrease inliningBenoît Ganne1-26/+19
Remove aggressive inlining outside of the main loop to improve build time (from 146s to 22s). Type: refactor Change-Id: I3824516a85b5e8d02894e66f19d891569c1a68fb Signed-off-by: Benoît Ganne <bganne@cisco.com>
2021-06-30rdma: fix chained buffer tx path in dv modeBenoît Ganne1-24/+20
When switching to the direct verb chain buffer tx path, we must account for all remaining packets, including the packets that would wrapped around. Previously we were using the 'n' counter but ignoring the 'n_wrap' counter: if some packets would have wrapped around in the default path, it would be ignored by the chained buffer tx path. Compute the correct number of remaining packets based on the old and current txq tail instead. Also simplify the chained tx function parameters. Type: fix Change-Id: If12b41a8f143fda80290342e2904792f7501c559 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2021-05-03rdma: avoid unnencessary inliningDamjan Marion1-27/+29
Type: fix Change-Id: Ifc4b30675365ebb5d69c018a34fd17a5090b30e1 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-11-25rdma: fixed UAR writing at txMohammed Hawari1-1/+1
Change-Id: Id81b4d27845c4e91cef90a4b8649662942d3cba1 Signed-off-by: Mohammed Hawari <mohammed@hawari.fr> Type: fix
2020-11-04rdma: various fixes for chained buffers txMohammed Hawari1-14/+19
Type: fix Signed-off-by: Mohammed Hawari <mohammed@hawari.fr> Change-Id: I428c87e581db335362fef30e274db8947a896416
2020-04-27rdma: tx: interleave prefetchesBenoît Ganne1-24/+13
Type: improvement Change-Id: Ic2d9b17cf5e524f3ad2a3c5343fe1230aa360e73 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2020-03-20rdma: ring db only once per vector on txBenoît Ganne1-28/+44
Type: improvement Change-Id: I09b017d60bc38ff8a4a7a73aff42b27611bd8955 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2020-03-16rdma: optimize tx wqe_initDamjan Marion1-11/+17
Type: improvement Change-Id: I7f28a3f03ab1ea8461c52743c61dc23a57965237 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-03-16rdma: introduce direct verb for Cx4/5 txBenoît Ganne1-45/+407
Direct Verb allows for direct access to NIC HW rx/tx rings. This patch introduce TX direct verb support for Mellanox ConnectX-4/5 adapters. 'dv' mode must be explicitely selected at interface creation to benefit from this. Type: feature Change-Id: If830ba9f33db73299acdbddc68b5c09eaf6add98 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2019-08-27rdma: fix pending packets check on txBenoît Ganne1-1/+1
Fix coverity CID 203636: Control flow issues (NO_EFFECT). This greater-than-or-equal-to-zero comparison of an unsigned value is always true. "n_left_from >= 0U". Type: fix Fixes: e7e8bf37f100b20acb99957572f1796f648c2853 Change-Id: Ibbf8c82defb12d6d532345eea657d5f300e6a514 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2019-08-26rdma: use rings for buffers managementBenoît Ganne1-53/+82
Refactor rdma driver for improved performance and prepare for raw datapath access. Type: refactor Change-Id: Iae31872055a6947708ea9f430bd1dc083ea63b5a Signed-off-by: Benoît Ganne <bganne@cisco.com>
2019-08-06rdma: fix double-free in rdma-txBenoît Ganne1-3/+4
In case of tx success after multiple retries, the last buffers to be enqueued will be both enqueued for tx and freed. Type: fix Fixes: 211ef2eb24 Change-Id: I57d218cff58b74c1f3d6dc5722624327f0821758 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2019-04-05rdma: more batching, compile rdma-core in release modeBenoît Ganne1-19/+41
rx: add batching for WC processing and release tx: improve batching for WC submission and processing rdma-core: compile in release mode to remove assert() Change-Id: I5fb8736db36b50f8b758cd688100477b67e72d80 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2019-04-03rdma: tx: fix stats and add batchingBenoît Ganne1-61/+88
Tx stats are no longer counted twice. Submit tx packets as a single batch per vector instead of per-packet Change-Id: I26820b21f23842b3a67ace0b939095f3550d3856 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2019-03-28Add RDMA ibverb driver pluginBenoît Ganne1-0/+133
RDMA ibverb is a userspace API to efficiently rx/tx packets. This is an initial, unoptimized driver targeting Mellanox cards. Next steps should include batching, multiqueue and additional cards. Change-Id: I0309c7a543f75f2f9317eaf63ca502ac7a093ef9 Signed-off-by: Benoît Ganne <bganne@cisco.com>