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2023-08-07vppinfra: add clib_file_get_resolved_basenameDamjan Marion1-1/+1
more generic version of clib_sysfs_link_to_name with support for format strings... Type: improvement Change-Id: I0cb263748970378c661415196eb7e08450370677 Signed-off-by: Damjan Marion <damarion@cisco.com>
2023-07-28vlib: pci cleanup and improvementsDamjan Marion1-12/+1
Change-Id: Ieafbed6f2db3dec65e4b43d84a4661f6a1bbe891 Type: improvement Signed-off-by: Damjan Marion <damarion@cisco.com>
2023-05-16misc: make format_hexdump length u32Benoît Ganne1-3/+2
format_hexdump currently requires the length parameter to be uword (64-bits) hence all callers must make sure to cast the length to uword. Use u32 instead to benefit from C automatic integer promotion: any length smaller or equal to u32 will be promoted to int fitting in u32). Only callers using a length of u64 needs to downcast. It also makes it similar to other variants. Type: fix Change-Id: I09b52fdde3970cec0be4150a29126ff63106c75b Signed-off-by: Benoît Ganne <bganne@cisco.com>
2023-04-27api: Mark old message versions as deprecatedOndrej Fabry1-0/+4
This change is part of VPP API cleanup initiative. Type: refactor Signed-off-by: Ondrej Fabry <ofabry@cisco.com> Change-Id: I9f0f786b50aa77383b16e0f844c85f236f7aa8d0
2023-04-21rdma: fix rx CQ mask to calculate right next_cqe_indexJieqiang Wang1-1/+1
Set the mask of calculating the next cqe index to the corresponding CQ size instead of rxq size. Type: fix Signed-off-by: Jieqiang Wang <jieqiang.wang@arm.com> Change-Id: I67494f029967af64051f51452eba1fd699984cd9
2023-04-11rdma: disable compressed CQE mode for txq CQJieqiang Wang1-3/+1
Previously we encountered the issue of failing to create completion queues on some Arm platforms because DPDK may set MLX5_CQE_SIZE to 128 if DPDK MLX PMDs are built and DPDK plugin is loaded, which does not satisfy the requirement of 64B size CQE by RDMA plugin. We fixed this issue in 844a0e8b0("always use 64 byte CQEs for MLX5"), but some of CSIT test cases failed due to this code change. It turns out that we don't need to specify compressed CQE mode for txq CQ because RDMA tx doesn't have the code logic to handle compressed CQEs, which might cause unexpected behavior if it is enabled. Type: fix Fixes: 844a0e8b0 ("always use 64 byte CQEs for MLX5") Signed-off-by: Jieqiang Wang <jieqiang.wang@arm.com> Change-Id: I7909a6d44b15bcf39c15dfac9377b65520a0cbfb
2023-02-13rdma: always use 64 byte CQEs for MLX5Nathan Brown1-5/+23
When DPDK MLX PMDs are built, and the DPDK plugin is loaded, DPDK may set the MLX5_CQE_SIZE environment variable to 128. This causes the RDMA plugin to be unable to create completion queues. Since the RDMA plugin expects the CQEs to be 64 bytes, set the cqe_size explicitly when creating the CQ. This avoids any issues with different values for the MLX5_CQE_SIZE environment variable. Type: improvement Signed-off-by: Nathan Brown <nathan.brown@arm.com> Change-Id: Idfd078d3045a4dcb674325ef36f85a89df6fbebc
2022-11-29rdma: fix for-loop initialization in scalar pathJieqiang Wang1-20/+35
When n_rx_packets is less then 16(VEC256) or 8(VEC128), code execution will fall into scalar path of processing packets. But with a wrong initialization value for n_left set to zero, i in the for-loop will equal to n_rx_packets. This leads to the bypass of required ip4 checksum validation and byte count endianness conversion in scalar path. Besides, refactor the code using while instead of for-loop to keep consistency with VPP code style. Type: fix Fixes: bf93670c515d ("rdma: fix ipv4 checksum check in rdma-input node") Signed-off-by: Lijian Zhang <lijian.zhang@arm.com> Signed-off-by: Jieqiang Wang <jieqiang.wang@arm.com> Change-Id: Ib4e8cb5202735f8b060c99caddf26035657551e1
2022-10-25rdma: set correct CQE flagsJieqiang Wang1-6/+6
CQE flags located in bits 16-31 at offset 0x1c should be defined as actual numbers instead of indexes. Besides, L3 header type for IPv4 is 10(2 in decimal) and for IPv6 is 01(1 in decimal) according to CQE entry fields description of page 120 in Mellanox Programmer Reference Manual. (https://network.nvidia.com/files/doc-2020/ethernet-adapters-programming-manual.pdf) Fixing this issue will lead to correct CQE flags printing for rdma-input node when buffer trace is enabled. Type: fix Signed-off-by: Jieqiang Wang <jieqiang.wang@arm.com> Change-Id: I9b578ca5cbd8cd93a577aa83131e31c79f60430e
2022-10-25rdma: fix ipv4 checksum check in rdma-input nodeJieqiang Wang1-23/+40
- cqe_flags pointer should be incremented accordingly otherwise only the first element in cqe_flags will be updated - flag l3_ok should be set for match variable when verifying if packets are IPv4 packets with flag l3_ok set - mask/match variables should be converted to network byte order to match the endianness of cqe_flags - vector processing of checking cqe flags will set return value to 0xFFFF by mistake if packet numbers are not multiple of 16(VEC256) or 8(VEC128) Type: fix Signed-off-by: Jieqiang Wang <jieqiang.wang@arm.com> Change-Id: I9fec09e449fdffbb0ace8e5a6ccfeb6869b5cac1
2022-10-04rdma: unhackish build of rdma-coreMohammed Hawari1-5/+3
Change-Id: I2040b560b2a00f8bd176ae6ad46035678a2b249e Type: improvement Signed-off-by: Mohammed Hawari <mohammed@hawari.fr>
2022-08-23rdma: fix coverity 249197Benoît Ganne1-2/+2
flags is u64, makes sure we do not overflow when shifting. Type: fix Change-Id: Ieea34187c0b568dc4d24c9415b9cff36907a5a87 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2022-05-05rdma: two small improvements for rdma interfaceJieqiang Wang2-5/+5
- fix branch prediction for checking rdma ERROR flag - add the missing right angle bracket to help message Type: improvement Signed-off-by: Jieqiang Wang <jieqiang.wang@arm.com> Reviewed-by: Lijian Zhang <lijian.zhang@arm.com> Reviewed-by: Tianyu Li <tianyu.li@arm.com> Change-Id: I2ce667631b3e3f60939069e2a16ddba0ff12a695
2022-01-18vnet: distinguish between max_frame_size and MTUDamjan Marion1-2/+3
Type: improvement Change-Id: I3659de6599f402c92e3855e3bf0e5e3388f2bea0 Signed-off-by: Damjan Marion <damarion@cisco.com>
2022-01-17interface: improve MTU handlingDamjan Marion1-6/+4
- per hw-interface-class handlers - ethernet set_mtu callback - driver can now refuse MTU change Type: improvement Change-Id: I3d37c9129930ebec7bb70caf4263025413873048 Signed-off-by: Damjan Marion <damarion@cisco.com>
2022-01-07ethernet: new interface registration functionDamjan Marion1-5/+7
Prep for supporting multiple callbacks, optional args, etc. Type: improvement Change-Id: I96244c098712e8213374678623f12527b0e7f387 Signed-off-by: Damjan Marion <damarion@cisco.com>
2022-01-05interface: refactor interface capabilities codeDamjan Marion1-3/+2
Make it shorter to type, easier to debug, make adding callbacks in future simpler. Type: improvement Change-Id: I6cdd6375e36da23bd452a7c7273ff42789e94433 Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-12-03api: refactor to use REPLY_MSG_ID_BASE #defineKlement Sekera1-10/+7
REPLY_MSG_ID_BASE is the standard way to define reply message id base, so this refactor makes all the files use that. This is a preparation patch for future safety add-ons which rely on REPLY_MACRO* parameters to be preprocessor tokens identifying the message instead, Type: refactor Signed-off-by: Klement Sekera <ksekera@cisco.com> Change-Id: Ibe3e056a3d9326d08af45bbcb25588b11e870141
2021-10-13docs: convert plugins doc md->rstNathan Skrzypczak2-75/+102
Type: improvement Change-Id: I7e821cce1feae229e1be4baeed249b9cca658135 Signed-off-by: Nathan Skrzypczak <nathan.skrzypczak@gmail.com>
2021-08-20rdma: decrease inliningBenoît Ganne1-26/+19
Remove aggressive inlining outside of the main loop to improve build time (from 146s to 22s). Type: refactor Change-Id: I3824516a85b5e8d02894e66f19d891569c1a68fb Signed-off-by: Benoît Ganne <bganne@cisco.com>
2021-07-15misc: replace CLIB_PREFETCH with clib_prefetch_{load,store}Damjan Marion1-4/+4
Type: refactor Change-Id: Id10cbf52e8f2dd809080a228d8fa282308be84ac Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-06-30rdma: fix chained buffer tx path in dv modeBenoît Ganne1-24/+20
When switching to the direct verb chain buffer tx path, we must account for all remaining packets, including the packets that would wrapped around. Previously we were using the 'n' counter but ignoring the 'n_wrap' counter: if some packets would have wrapped around in the default path, it would be ignored by the chained buffer tx path. Compute the correct number of remaining packets based on the old and current txq tail instead. Also simplify the chained tx function parameters. Type: fix Change-Id: If12b41a8f143fda80290342e2904792f7501c559 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2021-05-04rdma: add support for RSS configurationBenoît Ganne7-14/+338
Type: feature Change-Id: I911ee94b624ef5edf46b34666597eff93df1d1ed Signed-off-by: Benoît Ganne <bganne@cisco.com>
2021-05-04rdma: support non-power-of-2 number of rxqBenoît Ganne1-13/+19
Type: improvement Change-Id: I7b78a8470aa3fd271120587d08e82afb23cb195b Signed-off-by: Benoît Ganne <bganne@cisco.com>
2021-05-03rdma: avoid unnencessary inliningDamjan Marion1-27/+29
Type: fix Change-Id: Ifc4b30675365ebb5d69c018a34fd17a5090b30e1 Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-04-30build: declare some CMake variables as advancedDamjan Marion1-1/+1
Type: make Change-Id: I780c1c81a50cb92bc89c05856efd8ef88479c0ab Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-04-14rdma: remove redundant memory registrationBenoît Ganne1-6/+0
The memory region is already registered right above, looks like a copy/paste error. Type: fix Change-Id: I97aed821e719e1a34ac38c86d0473a8fdd671d4e Signed-off-by: Benoît Ganne <bganne@cisco.com>
2021-04-14rdma: fix skip_ipv4_cksum behavior in scalar pathTianyu Li1-1/+1
Current rdma input L3 validating behavior for scalar path is: if any packet L3_OK flag matches, then unset skip_ip4_cksum. The correct behavior should be if any packet L3_OK NOT match, then unset skip_ip4_cksum. The logic is also different from the vector path. This patch fixes the wrong behavior for scalar path. Type: fix Signed-off-by: Tianyu Li <tianyu.li@arm.com> Change-Id: I5ca5ed3aa0c07d441f3c87b33f03ea8f7a3c9826
2021-03-25rdma: fix buggy cqe parsing (truncated packets)Mohammed Hawari1-3/+2
Change-Id: I17228bd35cc7aa0d207a16502bf1376c75675302 Signed-off-by: Mohammed Hawari <mohammed@hawari.fr> Type: fix
2021-03-19interface: add capabilities flagsMohsin Kazmi1-2/+2
Type: improvement This patch adds flags to represent the modern NICs capabilities. Change-Id: I96d38d9ab7eac55974d72795cd100d8337168e1e Signed-off-by: Mohsin Kazmi <sykazmi@cisco.com>
2021-02-15rdma: rdma_log__ argument dev is a pointerVratko Polak1-5/+8
Also apply style edits as proprosed by checkstyle. Ticket: VPP-1971 Type: fix Change-Id: I4332a4e32220f3076b4a373da01cc0022cde32f5 Signed-off-by: Vratko Polak <vrpolak@cisco.com>
2021-01-21rdma: adapt to new vnet rxq frameworkMohammed Hawari3-27/+30
Change-Id: Id539d36635f0ab9625dc2fc73630be39bead09af Signed-off-by: Mohammed Hawari <mohammed@hawari.fr> Type: improvement
2020-11-25rdma: fixed UAR writing at txMohammed Hawari1-1/+1
Change-Id: Id81b4d27845c4e91cef90a4b8649662942d3cba1 Signed-off-by: Mohammed Hawari <mohammed@hawari.fr> Type: fix
2020-11-13rdma: implement multiseg rx without striding rqMohammed Hawari8-65/+470
Change-Id: I623617ad3c80610805dd3cf2a5f371e6677f4844 Signed-off-by: Mohammed Hawari <mohammed@hawari.fr> Type: improvement
2020-11-09vlib: fix trace number accountingBenoît Ganne1-15/+12
When using classifier to filter traces, not all packets will be traced. In that case, we should only count traced packets. Type: fix Change-Id: I87d1e217b580ebff8c6ade7860eb43950420ae78 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2020-11-04rdma: various fixes for chained buffers txMohammed Hawari1-14/+19
Type: fix Signed-off-by: Mohammed Hawari <mohammed@hawari.fr> Change-Id: I428c87e581db335362fef30e274db8947a896416
2020-10-26rdma: fix clang-11 buildDamjan Marion1-1/+1
/vpp/src/plugins/rdma/rdma.h:203:17: error: field 'buffer_template' with variable sized type 'vlib_buffer_t' not at the end of a struct or class is a GNU extension [-Werror,-Wgnu-variable-sized-type-not-at-end] vlib_buffer_t buffer_template; Type: fix Change-Id: I4661839f262e01fe274a2ee7b3cb70f9bc6b7c62 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-10-24rdma: implement striding rq for multiseg rxMohammed Hawari4-130/+433
This change leverages the striding RQ feature of ConnectX-5 adapters to support chained buffers on the RX path. In Striding RQ mode, WQE are SG lists of data segments, each mapped to a vlib_buffer. When a packet is received, it can consume one or multiple data segments belonging to the WQE, without wasting the whole WQE. Change-Id: I74eba5b2c2c66538e75e046335058ba011cb27fd Type: improvement Signed-off-by: Mohammed Hawari <mohammed@hawari.fr>
2020-10-24rdma: add RSS support for IPv6 and TCPBenoît Ganne2-32/+58
Type: feature Change-Id: I8b0d918e6f13325954b29bf34e4ef224c1315c51 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2020-08-31rdma: bugfix in the descriptor refill logic. In case of a partial ↵Mohammed Hawari1-1/+1
allocation, the remainder modulo 8 must be returned to the pool so that the number of kept buffers is a multiple of 8. Type: fix Change-Id: Ifd97b03ea220300e7e6fe81a8ff4a25060fea6c1 Signed-off-by: Mohammed Hawari <mohammed@hawari.fr>
2020-05-27ethernet: fix DMAC check and skip unnecessary ones (VPP-1868)John Lo1-4/+13
Fix and optimize DMAC check in ethernet-input node to utilize NIC or driver which support L3 DMAC-filtering mode so that DMAC check can be bypassed safely for interfaces/sub-interfaces in L3 mode. Checking of interface in L3-DMAC-filtering state to avoid DMAC check require the following: a) Fix interface driver init sequence for devices which supports L3 DMAC-filtering to indicate its capability and initialize interface to L3 DMAC-filtering state. b) Fix ethernet_set_flags() function and its associated callback flags_change() functions registered by various drivers in interface infra to provide proper L3 DMAC filtering status. Maintain interface/sub-interface L3 config count so DMAC checks can be bypassed if L3 forwarding is not setup on any main/sub-interfaces. Type: fix Ticket: VPP-1868 Signed-off-by: John Lo <loj@cisco.com> Change-Id: I204d90459c13e9e486cfcba4e64e3d479bc9f2ae
2020-05-07rdma: fix alignment issueDamjan Marion1-2/+2
Type: fix Change-Id: I0ff7a6f3354066c2252c1ebd0d43ac59db278bf0 Signed-off-by: Damjan Marion <damarion@cisco.com> Signed-off-by: Elias Rudberg <elias.rudberg@bahnhof.net>
2020-05-06rdma: fix clang buildBenoît Ganne1-2/+9
Type: fix Change-Id: I9b613f0af484f601dd20a851e2f59ee5e06b5c37 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2020-04-27rdma: tx: interleave prefetchesBenoît Ganne1-24/+13
Type: improvement Change-Id: Ic2d9b17cf5e524f3ad2a3c5343fe1230aa360e73 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2020-03-31rdma: print device info from PCI VPD in 'show hardware' outputDamjan Marion1-0/+14
Type: improvement Change-Id: I275bbca17c5a0263b3e017b48aa6ccd8f59bc7c3 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-03-20rdma: ring db only once per vector on txBenoît Ganne1-28/+44
Type: improvement Change-Id: I09b017d60bc38ff8a4a7a73aff42b27611bd8955 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2020-03-16rdma: optimize tx wqe_initDamjan Marion3-13/+33
Type: improvement Change-Id: I7f28a3f03ab1ea8461c52743c61dc23a57965237 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-03-16rdma: introduce direct verb for Cx4/5 txBenoît Ganne4-73/+549
Direct Verb allows for direct access to NIC HW rx/tx rings. This patch introduce TX direct verb support for Mellanox ConnectX-4/5 adapters. 'dv' mode must be explicitely selected at interface creation to benefit from this. Type: feature Change-Id: If830ba9f33db73299acdbddc68b5c09eaf6add98 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2020-03-16rdma: add Mellanox mlx5 Direct Verbs receive supportDamjan Marion6-37/+843
Type: feature Change-Id: I3f287ab536a482c366ad7df47e1c04e640992ebc Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-03-02rdma: improve rx loopDamjan Marion1-38/+16
Type: improvement Change-Id: If81847bc0c92d167ce03e1e94a2f8e18f8154af2 Signed-off-by: Damjan Marion <damarion@cisco.com>