Age | Commit message (Collapse) | Author | Files | Lines |
|
The memory areas storing vlib_buffer_t and ip4|6_and_esp_header_t
are not prefetched. The patch help dpdk_esp_encrypt to reduce 18
clocks/pkt from 149 to 131 on Haswell when running IPsec in tunnel
mode.
Change-Id: I4f4e9e2b3982a4b7810cab8ed828a5e4631f8f8c
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
|
|
Change-Id: I6934beaf5c08bae2d4f0bd3a6bb811810407c1f9
Signed-off-by: Florin Coras <fcoras@cisco.com>
|
|
- Add subpages definitions in appropriate
section (User or Dev docs) for doc files
(*.rst, *.md) that being listed at the top
level of the generated doc page.
- Generate and add API list to RELEASE doc.
- Fix list_api_changes script to use HEAD
as the endtag so it doesn't need to be
changed every release.
Change-Id: Iace7b6433359c6b96869cb1db01facbbcb0ac1e6
Signed-off-by: Dave Wallace <dwallacelf@gmail.com>
(cherry picked from commit 11ee93f6abfaddf5bbd56cf0858c0c6ea0384b65)
|
|
Change-Id: Iac9ac9f5a6873aae1882316af4f6c919788a0cef
Signed-off-by: Florin Coras <fcoras@cisco.com>
|
|
Avoid creating per PPPoE session interface output/tx nodes
which are not used.
Change-Id: I065aa4f9bda6d2557c630bd45e888c999f2f9130
Signed-off-by: John Lo <loj@cisco.com>
|
|
Change-Id: Ia56cad89b85b7a99ab4bfb85318a45a71381fb53
Signed-off-by: Florin Coras <fcoras@cisco.com>
|
|
Some GBP debug cli short help and commands were not in sync anymore with
GBP API.
Change-Id: I224bec51fbacd8a3685b70d4e7a52b5803fd3ad4
Signed-off-by: Benoît Ganne <bganne@cisco.com>
|
|
Fifos can use multiple memory chunks for simple read/write operations.
Adding/removing chunks after assignment not yet supported.
Change-Id: I2aceab6aea78059d74e0d3a9993c40d5196d077b
Signed-off-by: Florin Coras <fcoras@cisco.com>
|
|
Change-Id: I11ac3e4f59206902e5dfc326f815c877c5dd6643
Signed-off-by: Florin Coras <fcoras@cisco.com>
|
|
Remove duplicate error check
Change-Id: I64463c7f606e198fe8553efea294f0e09bd8dbc3
Signed-off-by: Dave Barach <dave@barachs.net>
|
|
Change-Id: I65b1af5fa0cec4f9789f91f720d1396d06fa0206
Signed-off-by: Simon Zhang <yuwei1.zhang@intel.com>
|
|
Change-Id: I670d7899bcc63a419daf481167dc445a6386cce8
Signed-off-by: Neale Ranns <nranns@cisco.com>
|
|
As DVN has fewer DTLB entries supported for 2M page, default numbers of
RX/TX descriptors are changed to 512 if nums of RX/TX descriptors are not
specified by VPP users.
Change-Id: I076493b802b15d12750a5b49d1554da4d19ad460
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
|
|
Change-Id: I51f61a399e3eace93011f9431cbd7968e9be627c
Signed-off-by: Mohsin Kazmi <sykazmi@cisco.com>
|
|
Good enough to serve the vpp sphinx and doxygen docs. Knows about
html, css, and javascript files.
Change-Id: Ib18c19f07f35f91ba935ea26ed7be406dacf2205
Signed-off-by: Dave Barach <dave@barachs.net>
|
|
Problems Addressed:
- Contention of cursize by producer and consumer.
- Reduce the no of modulo operations.
Changes:
- Synchronization between producer and consumer changed from cursize
to head and tail indexes
Implications: reduces the usable size of fifo by 1.
- Using weaker memory ordering C++11 atomics to access head and tail
based on producer and consumer role.
- Head and tail indexes are unsigned 32 bit integers. Additions and
subtraction on them are implicit 32 bit Modulo operation.
- Adding weaker memory ordering variants of max_enq, max_deq, is_empty
and is_full Using them appropriately in all places.
Perfomance improvement (iperf3 via Hoststack):
iperf3 Server: Marvell ThunderX2(AArch64) - iperf3 Client: Skylake(x86)
~6%(256 rxd/txd) - ~11%(2048 rxd/txd)
Change-Id: I1d484e000e437430fdd5a819657d1c6b62443018
Signed-off-by: Sirshak Das <sirshak.das@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
|
|
To connect a stream, apps should call connect while passing the id of the QUIC
connection in the new transport_opts field in session_endpoint_cfg_t.
Apps are notified of new streams with their accept callback, which is called
each time a peer opens a stream.
Change-Id: I0f82ec344db58008d54641553eddec2973768435
Signed-off-by: Aloys Augustin <aloaugus@cisco.com>
|
|
Change-Id: Id2ddb77b4ec3dd543d6e638bc882923f2bac011d
Signed-off-by: Neale Ranns <nranns@cisco.com>
|
|
Change-Id: I48cd8052f9509efdf13f64ab279edb66a2d4a0a9
Signed-off-by: Simon Zhang <yuwei1.zhang@intel.com>
|
|
Change-Id: I832e780b00955e01871874544f3d0afc553b75f7
Signed-off-by: Dave Barach <dave@barachs.net>
|
|
Algorithm from CLRS, Introduction to Algorithms 3rd Edition, Ch. 13
Change-Id: I5bc2c507593770939cd5584f21dacf36ebd2b4c1
Signed-off-by: Florin Coras <fcoras@cisco.com>
|
|
Change-Id: Idfcf1644952d647c6e1b61216d9b365d58b77814
Signed-off-by: Simon Zhang <yuwei1.zhang@intel.com>
|
|
Change-Id: Id9dfd912517c44cf812953bd05ac04c9e172a2b7
Signed-off-by: Filip Tehlar <ftehlar@cisco.com>
|
|
Change-Id: Ib80e9bfb19a79e1adc79aef90371a15954daa993
Signed-off-by: Neale Ranns <nranns@cisco.com>
|
|
Change-Id: I749c5a9d58128fd6d0fb8284e56b8f89cf91c609
Signed-off-by: Neale Ranns <nranns@cisco.com>
|
|
Change-Id: I7d84bab7768421ed37813702c0413e52167f41ab
Signed-off-by: Filip Tehlar <ftehlar@cisco.com>
|
|
Change-Id: Ia86387ca5a52d6b4b9e5aff0c01c92df13a5dde5
Signed-off-by: Parixit Gokhale <pgokhale@cisco.com>
|
|
Change-Id: Ibb3e2f3ba5f31482fc2f0dce53d68f8476608f4b
Signed-off-by: Filip Tehlar <ftehlar@cisco.com>
|
|
hard code IV and key lengths based on cipher.
Init IV from random data, use AES instruction to rotate.
Change-Id: I13a6507d12267b823c528660a903787baeba47a0
Signed-off-by: Neale Ranns <nranns@cisco.com>
|
|
Change-Id: I49c710c5ace24a4c1f083120fd4c2972566a1695
Signed-off-by: Damjan Marion <damarion@cisco.com>
Signed-off-by: Filip Tehlar <ftehlar@cisco.com>
|
|
Add binary api and debug cli support.
Rewrite for speed: enqueue vlib_buffer_t's to the wheel, instead of
memcpy'ing data. Quad-loop the output feature / x-connect (interior)
node. Prefetch wheel entries in the input node.
Save packet-generator-based unit-test setup in extras/nsim.
Simple config example:
set nsim delay 20 ms bandwidth 1 gbit packet-size 1024
nsim output-feature enable-disable GigabitEthernet3/0/0
Change-Id: I852a32d4eb596e7e2aa1d9b30bf3b53525e39fd1
Signed-off-by: Dave Barach <dave@barachs.net>c
|
|
A plugin to use Intel IPSec MB library as a VPP crypto engine
This changes uses concepts from:
https://gerrit.fd.io/r/#/c/17301/
hence that author's work is acknowledge below
Change-Id: I2bf3beeb10f3c9706fa5efbdc9bc023e310f5a92
Signed-off-by: Neale Ranns <nranns@cisco.com>
Signed-off-by: Klement Sekera <ksekera@cisco.com>
|
|
Some API action handlers called vl_msg_ai_send_shmem()
directly. That breaks Unix domain socket API transport.
A couple (bond / vhost) also tried to send a sw_interface_event
directly, but did not send the message to all that had
registred interest. That scheme never worked correctly.
Refactored and improved the interface event code.
Change-Id: Idb90edfd8703c6ae593b36b4eeb4d3ed7da5c808
Signed-off-by: Ole Troan <ot@cisco.com>
|
|
Add dummy function to avoid session layer warning. Also, decrease
default debug level to avoid startup quic init notifications.
Change-Id: I2964fc15a8d93d78c976ed7c333e0cc5746c069e
Signed-off-by: Florin Coras <fcoras@cisco.com>
|
|
Add support for multiqueue for RDMA devices.
Change-Id: I78a2481cec6747494c670cc776475828be3af55b
Signed-off-by: Benoît Ganne <bganne@cisco.com>
|
|
When using the output feature ('postrouting') outbound translation,
no packets are passed when using worker threads. The frame queue for
in2out packets to be handed off between threads is never allocated.
This is because that allocation only happens if the value of
fq_in2out_output_index == ~0, but fq_in2out_output_index is never
initialized prior to checking that.
Initialize fq_in2out_output_index to ~0 so a frame queue will be
allocated when there are worker threads.
Change-Id: I0836685eb611348643c11ac7e4d0cab935a29384
Signed-off-by: Matthew Smith <mgsmith@netgate.com>
|
|
Change-Id: Ib436512a26e53f70f7b5e47bf34224ab73e5244e
Signed-off-by: Neale Ranns <nranns@cisco.com>
|
|
Change-Id: I215e1e0208a073db80ec6f87695d734cf40fabe3
Signed-off-by: Jim Thompson <jim@netgate.com>
|
|
VPP rdma driver relies on an internal rdma-core not compatible with DPDK
MLX driver. Force the use of external rdma-core through
RTE_IBVERBS_LINK_DLOPEN DPDK build option and make sure internal
rdma-core symbols are not leaked outside of the rdma plugin.
Change-Id: I5b2281259f517c4e109d388d172b72eadd69986f
Signed-off-by: Benoît Ganne <bganne@cisco.com>
|
|
Change-Id: I271aa8b8f4917c187ad52db774e4ad26677e2b82
Signed-off-by: Neale Ranns <nranns@cisco.com>
|
|
Change-Id: Ic6e23f497fd91dcb1441f9f4d88a182712e69d3f
Signed-off-by: Neale Ranns <nranns@cisco.com>
|
|
Change-Id: Iff6f81a49b9cff5522fbb4914d47472423eac5db
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Change-Id: I9db1b74097c9df587b9265b14a969d347bcb731a
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Change-Id: I5b18cb84bec88f5514cacd2df61b5ce3c70abd77
Signed-off-by: Mohsin Kazmi <sykazmi@cisco.com>
|
|
Change-Id: I8cb03ee832e77d2b21d47aa7a44579c283fb1054
Signed-off-by: Florin Coras <fcoras@cisco.com>
|
|
Change-Id: I0aa220b1f5a72d8bbc6d147830766790d7f6d9bf
Signed-off-by: Florin Coras <fcoras@cisco.com>
|
|
Change-Id: Ie8dcd9fa0d0487b146eaa62113a5ee06bd3e7d3b
Signed-off-by: Filip Tehlar <ftehlar@cisco.com>
|
|
rx: add batching for WC processing and release
tx: improve batching for WC submission and processing
rdma-core: compile in release mode to remove assert()
Change-Id: I5fb8736db36b50f8b758cd688100477b67e72d80
Signed-off-by: Benoît Ganne <bganne@cisco.com>
|
|
Change-Id: I438ef1f50d83560ecc608f898cfc61d7f51e1724
Signed-off-by: Damjan Marion <damarion@cisco.com>
|
|
Change-Id: I28bb9e3d3ea3a99a9e24801ef5241a0099186108
Signed-off-by: Neale Ranns <nranns@cisco.com>
|