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Looks like CPU doesn't like overlaping loads.
This new codes in some cases shows 3-4 clock improvements.
Change-Id: Ia1b49976ad95140c573f892fdc0a32eebbfa06c8
Signed-off-by: Damjan Marion <damarion@cisco.com>
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It'll be interesting to see what the perf trend job
says about this change.
Change-Id: I66307a19a865011ac9660108098874fa1481c895
Signed-off-by: Dave Barach <dave@barachs.net>
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bihash_48_8 case:
Scalar code: 6 clocks
SSE4.2 code: 3 clocks
AVX2 code: 2.27 clocks
AVX512 code: 1.5 clocks
Change-Id: I40700175835a1e7321276e47eadbf9771d3c5a68
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: I30a3df53bc5fe5ab991a657918eb502bd2913440
Signed-off-by: Andrew Yourtchenko <ayourtch@gmail.com>
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