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path: root/src/vppinfra/bihash_8_8.h
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2018-07-20Fine-grained add / delete lockingDave Barach1-2/+0
Add a bucket-level lock bit. Use a spinlock only when actually allocating, freeing, or splitting a bucket. Should improve multi-thread add/del performance. Change-Id: I3e40e2a8371685457f340d6584dea14e3207f2b0 Signed-off-by: Dave Barach <dave@barachs.net>
2017-08-31Fix BIHASH_KVP_CACHE_SIZE == 0 caseDave Barach1-1/+1
Setting the bucket-level LRU cache size to zero removes the bucket-level LRU cache code. Change-Id: Idf2e63d0d508675e957366515863766f79a3479c Signed-off-by: Dave Barach <dbarach@cisco.com>
2017-07-19Add a bihash prefetchable bucket-level cacheDave Barach1-0/+3
According to Maciek, the easiest way to leverage the csit "performance trend" job is to actually merge the patch once verified. Manual testing indicates that the patch improves l2 path performance. Other use-cases are TBD. It's possible that we'll need to back out the patch depending on what happens. Change-Id: Ic0a0363de35ef9be953ad7709c57c3936b73fd5a Signed-off-by: Dave Barach <dave@barachs.net>
2017-07-13Use clib_crc32c_uses_intrinsics instead of __SSE4_2__Christophe Fontaine1-1/+1
clib_crc32c is not limited to x86 platforms. Change-Id: I5f6d5fdd4af80f9fe696d3317453fa58760df1db Signed-off-by: Christophe Fontaine <christophe.fontaine@enea.com>
2017-05-10Add crc32c inline function, allows compilation on 32-bit systemsDamjan Marion1-5/+2
32-bit code still can use crc32c instructions, but it operates on 32 registers Change-Id: I9bb6b0b59635d6ea6a753584676ebcf59c8f6584 Signed-off-by: Damjan Marion <damarion@cisco.com>
2017-01-02Handle execessive hash collisions, VPP-555Dave Barach1-0/+1
Change-Id: I55dad7b5cfb3d38c22b1105f7d2d61e7449410ea Signed-off-by: Dave Barach <dave@barachs.net>
2016-12-28Reorganize source tree to use single autotools instanceDamjan Marion1-0/+98
Change-Id: I7b51f88292e057c6443b12224486f2d0c9f8ae23 Signed-off-by: Damjan Marion <damarion@cisco.com>