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path: root/src/vppinfra/cpu.c
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2023-04-17vppinfra: add AMD EPYC cpu family detailsSivaprasad Tummala1-2/+23
Type: feature - Added support for AMD EPYC processor family Change-Id: I60da87cca429117c209d240e5a5f3b4d9f4981d8 Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
2022-01-24vppinfra: fix compilation on riscvDamjan Marion1-8/+10
Type: fix Change-Id: I2bc58a711c9429d7989bfd0bfccd289d43fc35d0 Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-11-23vppinfra: update CPU listDamjan Marion1-47/+52
Type: improvement Change-Id: Ibe1f23801d5eac6d1dae61c6df1a47d59455d42e Signed-off-by: Damjan Marion <dmarion@me.com>
2021-05-07vppinfra: add universal array mask_compare and compress funcsDamjan Marion1-0/+12
Type: improvement Change-Id: I6d812339f626ea630ad9354632d2f9506122d379 Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-04-18vppinfra: remove linux/syscall.hDamjan Marion1-0/+14
For portabiliy reasons it is better to have all wrapped in clib code. I.e. instead of using getcpu() we have clib_get_current_numa_node () and clib_get_current_cpu_id(). Type: refactor Change-Id: I29b52d7f29bc7f93873402c4070561f564b71c63 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-10-17vppinfra: explicitly export symbolsDamjan Marion1-3/+3
Type: improvement Change-Id: I57a9f85f7df1fc48656b72592349f4c544302f77 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-02-11vppinfra: add ARM cpu typesDamjan Marion1-0/+4
Type: improvement Change-Id: Ib2cb708fdcb14fdea9298c10d67f8fe73887f18b Signed-off-by: Damjan Marion <dmarion@me.com>
2020-01-27vppinfra: add x86 CPU definitionsDamjan Marion1-0/+8
Type: feature Change-Id: I9d1f9f00ac011a93709850186dcf4cf5ea3bf88a Signed-off-by: Damjan Marion <damarion@cisco.com>
2019-12-17vppinfra: fix cpu flag string overflowBenoît Ganne1-7/+5
Type: fix Change-Id: Idb1fff8a172034044bb33d5b271a84d1fd672ef5 Signed-off-by: Benoît Ganne <bganne@cisco.com>
2019-08-19vppinfra: Update "show cpu" output for AArch64 chipsNitin Saxena1-15/+18
- Allow "Microarch model(family)" row to show PASS revison as either string (like A0, B0) or number (like 1.0, 2.0). - Fix part number for Marvell CN96XX Change-Id: Ie01a3960c4e5e481be354dc8bb60f744e5c65737 Signed-off-by: Nitin Saxena <nsaxena@marvell.com>
2019-01-02Add microarch details to 'show cpu'.Paul Vinciguerra1-2/+4
Change-Id: I31a3ff9e8f70468196c091027592a3aed2d09ac3 Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com>
2018-01-06aarch64 - show cpu microarchitectureGabriel Ganne1-0/+50
Combine implementer, part, variant, and revision into one cpu description line. For example : ARM (Cortex-A57 PASS 1.2) * get infos from /proc/cpuinfo * only recognize armv8 processors * add all given cavium processors * Cavium starts counting variants from 1 instead of 0 Change-Id: I4f3820fb13a6bd2a0dc59e28fbe6f48a5b0ceb25 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-12-05fill "show cpu" Flag list on aarch64 platforms (VPP-1065)Gabriel Ganne1-2/+19
use getauxval(AT_HWCAP) to get the processor capabilities. The result should be the same as calling cat /proc/cpuinfo | grep Feature | head -n1 All but one (aes) features have a different name. handle aes by adding it an arch prefix, which is skipped during print and a clib_cpu_supports_aes() custom function. Change-Id: If9830bd5a17bac1bd1b5337dacbb0ddbb8ed6b18 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-11-11Update CPU listDamjan Marion1-17/+35
Change-Id: Ibee8973270366c38dced6eb3e8ca41784549183a Signed-off-by: Damjan Marion <damarion@cisco.com>
2016-12-28Reorganize source tree to use single autotools instanceDamjan Marion1-0/+133
Change-Id: I7b51f88292e057c6443b12224486f2d0c9f8ae23 Signed-off-by: Damjan Marion <damarion@cisco.com>