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2019-08-19vppinfra: Update "show cpu" output for AArch64 chipsNitin Saxena1-15/+18
- Allow "Microarch model(family)" row to show PASS revison as either string (like A0, B0) or number (like 1.0, 2.0). - Fix part number for Marvell CN96XX Change-Id: Ie01a3960c4e5e481be354dc8bb60f744e5c65737 Signed-off-by: Nitin Saxena <nsaxena@marvell.com>
2019-01-02Add microarch details to 'show cpu'.Paul Vinciguerra1-2/+4
Change-Id: I31a3ff9e8f70468196c091027592a3aed2d09ac3 Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com>
2018-01-06aarch64 - show cpu microarchitectureGabriel Ganne1-0/+50
Combine implementer, part, variant, and revision into one cpu description line. For example : ARM (Cortex-A57 PASS 1.2) * get infos from /proc/cpuinfo * only recognize armv8 processors * add all given cavium processors * Cavium starts counting variants from 1 instead of 0 Change-Id: I4f3820fb13a6bd2a0dc59e28fbe6f48a5b0ceb25 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-12-05fill "show cpu" Flag list on aarch64 platforms (VPP-1065)Gabriel Ganne1-2/+19
use getauxval(AT_HWCAP) to get the processor capabilities. The result should be the same as calling cat /proc/cpuinfo | grep Feature | head -n1 All but one (aes) features have a different name. handle aes by adding it an arch prefix, which is skipped during print and a clib_cpu_supports_aes() custom function. Change-Id: If9830bd5a17bac1bd1b5337dacbb0ddbb8ed6b18 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-11-11Update CPU listDamjan Marion1-17/+35
Change-Id: Ibee8973270366c38dced6eb3e8ca41784549183a Signed-off-by: Damjan Marion <damarion@cisco.com>
2016-12-28Reorganize source tree to use single autotools instanceDamjan Marion1-0/+133
Change-Id: I7b51f88292e057c6443b12224486f2d0c9f8ae23 Signed-off-by: Damjan Marion <damarion@cisco.com>