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Change-Id: I79f65d7bd19af035442dca48b7be6c94de20c167
Signed-off-by: Florin Coras <fcoras@cisco.com>
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Use of scalar AVX512 instructions impacts the maximum CPU frequency
as they require CPU to request level 1 power license.
So sparse use of AVX512 like we do, typically causes more harm than
improvement.
This patch makes AVX2 higher priority than AVX512, but still there
is option to change it on per-node basis:
vpp# set node function ethernet-input avx512
Change-Id: I42e03510a6efc1756e22fbb70e8c76d7f74f59d7
Signed-off-by: Damjan Marion <damarion@cisco.com>
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It is causing compilation sloness with gcc-7 so removing it
before it was originally planned.
So far macros are left in the tree so we can know which nodes to
convert to new multiarch code.
Change-Id: Idb14622ca61fdce1eba59723b20d98715b7971e6
Signed-off-by: Damjan Marion <damarion@cisco.com>
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This patch introduces following changes:
- deprecated free lists which are not used and not compatible
with external buffer managers (i.e. DPDK)
- introduces native support for per-numa buffer pools
- significantly improves performance of buffer alloc and free
Change-Id: I4a8e723ae47056717afd6cac0efe87cb731b5be7
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: I79b213b34c6071d14acf1922f89037a4a5a36c45
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: If88ccd965122b9318a39a8d71b53334cd1fd81e4
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: I5b4cd419d317381a06e7e6d703373959f4bbd97b
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Currently, there are three variants available on aarch64, qdf24xx, thunderx2t99, and cortex-a72.
-DCLIB_N_PREFETCHES is passed to source code to select dual/quad implementation.
Besides, different compiler options are applied on these critical functions.
gcc-7.3.0 reports ICE(internal compiler error) with -mtune=thunderx2t99,
so -mtune=thunderx2t99 is enabled only when gcc version is greater than 7.3.0
Cavium ThunderX2, Impermenter 0x43, Part 0x0af
-march=armv8-a+crc+crypto -mtune=thunderx2t99
Qualcomm Centriq 2400, Impermenter 0x51, Part 0xc00
-march=armv8.1-a+crc+crypto -mtune=qdf24xx
Cortex-A72, Impermenter 0x41, Part 0xd08
-march=armv8-a+crc+crypto -mtune=cortex-a72
Change-Id: Id5649c6325c1e642d0fd42535e3908793b13e02a
Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com>
Reviewed-by: Sirshak Das <sirshak.das@arm.com>
Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
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Change-Id: Ifa4fceef7edbe43d444790a624957db0817064de
Signed-off-by: Florin Coras <fcoras@cisco.com>
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Change-Id: Ibab5e27277f618ceb2d543b9d6a1a5f191e7d1db
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: Ia1b49d7fd5f32d9a5139df5df636b46264003a63
Signed-off-by: Damjan Marion <damarion@cisco.com>
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use getauxval(AT_HWCAP) to get the processor capabilities.
The result should be the same as calling
cat /proc/cpuinfo | grep Feature | head -n1
All but one (aes) features have a different name.
handle aes by adding it an arch prefix, which is skipped during print
and a clib_cpu_supports_aes() custom function.
Change-Id: If9830bd5a17bac1bd1b5337dacbb0ddbb8ed6b18
Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
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Change-Id: If581feca0d51d0420c971801aecdf9250c671b36
Signed-off-by: Damjan Marion <damarion@cisco.com>
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Change-Id: I7b51f88292e057c6443b12224486f2d0c9f8ae23
Signed-off-by: Damjan Marion <damarion@cisco.com>
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