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path: root/src/vppinfra/vector_sse42.h
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2022-02-10vppinfra:remove uXxY_is_greaterDamjan Marion1-6/+0
not needed, '>' works... Type: improvement Change-Id: I9bfbac787e8dca24e9b1bceda0922740eed26346 Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-12-02vppinfra: vector shuffle cleanupDamjan Marion1-18/+0
Type: refactor Change-Id: I8b3fc2ce30df313467274a174c5ac6adbf296153 Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-07-14vppinfra: remove old and unused vector macros and inlinesDamjan Marion1-197/+0
Type: refactor Change-Id: Ic504bcfca6e7fbd85e858c3bc7a4f5e72d931789 Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-05-05vppinfra: fix x86 packs / packus wrappersDamjan Marion1-66/+10
They both take signed value as input. Type: fix Change-Id: If3d8ec4e0b1c02d7d65262bdd9db49ff7fbfef39 Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-04-27vlib: improve enqueue_to_next buffer indices extractionDamjan Marion1-0/+6
Type: improvement Change-Id: Ib7b2fa7d821f6d2708f6dc378a0f36f68c843f57 Signed-off-by: Damjan Marion <damarion@cisco.com>
2021-04-25vppinfra: AVX512 mask load/stores and compress storeDamjan Marion1-8/+0
Type: improvement Change-Id: Id6be598aade072653e408cca465e62931d060233 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-08-31vppinfra: convert A_extend_to_B to B_from_A format of vector inlinesDamjan Marion1-2/+2
Make it shorter and same format when converting to biggor or smaller types. Type: refactor Change-Id: I443d67e18ae65d779b4d9a0dce5406f7d9f0e4ac Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-07-15vppinfra: more vector inlinesDamjan Marion1-0/+16
Type: improvement Change-Id: Ie0de374b89ec3a17befecf3f08e94951597609ec Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-06-23vppinfra: fix u32x4_gather definitionDamjan Marion1-1/+1
Type: fix Change-Id: I3df8d3f277bfadee95bfc329e8ce8b929a986af6 Signed-off-by: Damjan Marion <damarion@cisco.com>
2020-02-13vppinfra: add 128-bit and 512-bit a ^ b ^ c shortcutDamjan Marion1-0/+9
This allows us to combine 2 XOR operations into signle instruction which makes difference in crypto op: - in x86, by using ternary logic instruction - on ARM, by using EOR3 instruction (available with sha3 feature) Type: refactor Change-Id: Ibdf9001840399d2f838d491ca81b57cbd8430433 Signed-off-by: Damjan Marion <damjan.marion@gmail.com>
2020-02-13crypto-native: add AArch64 AES-GCM native implementationDamjan Marion1-0/+9
Type: feature Change-Id: I4f96b0af13b875d491704b010328a1814e1dbda1 Signed-off-by: Damjan Marion <dmarion@me.com>
2019-04-15vppinfra: add SHA-2 family of hash algorithms (including HMAC)Damjan Marion1-0/+9
Change-Id: I54d6fb1a2721b548620eb66cea254d0103deca32 Signed-off-by: Damjan Marion <damarion@cisco.com>
2019-04-02vppinfra: add u32x4 min / max sse4.2 inlinesDamjan Marion1-24/+49
Change-Id: I38e0be777199654ece286fdd1a42931ed99bbe8a Signed-off-by: Damjan Marion <damarion@cisco.com>
2019-03-26ipsec: esp-encrypt reworkDamjan Marion1-0/+12
Change-Id: Ibe7f806b9d600994e83c9f1be526fdb0a1ef1833 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-11-20vppinfra: add 128 and 256 bit vector scatter/gather inlinesDamjan Marion1-0/+43
Change-Id: If6c65f16c6fba8beb90e189c1443c3d7d67ee02c Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-17CMake as an alternative to autotools (experimental)Damjan Marion1-1/+1
Change-Id: Ibc59323e849810531dd0963e85493efad3b86857 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-07-27Fix build-break when compiling -O0 / TAG=vpp_debugDave Barach1-1/+1
Without inlining [TAG=vpp_debug], gcc7 (at least) refuses to produce the indicated vector unit instruction. Change-Id: I0f0400ad74b1e498dce7963a85c47d33afe0a768 Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-27128-bit SIMD version of vlib_get_buffersDamjan Marion1-0/+36
Change-Id: I1a28ddf535c80ecf4ba4bf31659ff2fead1d8a64 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-07-26vppinfra: add SSE4.2 version of u8x16_shuffleDamjan Marion1-0/+6
Change-Id: I4bf1cfe5a9492092a7362675079c47629b6f0ee8 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-06-27vppinfra: add vector horizontal add and byte swap (SSE4.2 & AVX2)Damjan Marion1-0/+15
Change-Id: I4e0fd487970796f0153a5b16333827d23b57deac Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-05-22vppinfra: add clib_count_equal_uXX and clib_memset_uXX functionsDamjan Marion1-2/+2
Change-Id: I56782652d8ef10304900cc293cfc0502689d800e Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-05-20vector functions cleanup and improvementsDamjan Marion1-38/+46
Remove functions which have native C equivalent (i.e. _is_equal can be replaced with ==, _add with +) Add SSE4.2, AVX-512 implementations of splat, load_unaligned, store_unaligned, is_all_zero, is_equal, is_all_equal Change-Id: Ie80b0e482e7a76248ad79399c2576468532354cd Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-05-19Disable vector code in vlib_buffer_enqueue_to_next if no msb mask functionDamjan Marion1-0/+2
This fixes ARM64 build where we dont have defined u16x8_msb_mask(...) Change-Id: I864f5134a0d951601810c800f587d173b3b7ef41 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-05-18Add vlib_buffer_enqueue_to_next inline functionDamjan Marion1-0/+6
Change-Id: I1042c0fe179b57a00ce99c8d62cb1bdbe24d9184 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-04-25dpdk: complete rework of the dpdk-input nodeDamjan Marion1-2/+2
Change-Id: If174d189de40e6f9ffae99997bba93a2519d9fda Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-20vppinfra: autogerate vector typedefs and basic inline functionsDamjan Marion1-143/+0
Change-Id: Ie9f611fa6a962b0937245f5cc949571ba11c5604 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-20vppinfra: CLIB_HAVE_VEC128 mandates SSE4.2Damjan Marion1-0/+730
Change-Id: I6511110d0472203498a4f8741781eeeeb4f90844 Signed-off-by: Damjan Marion <damarion@cisco.com>