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2018-09-02cmake: cache line size detectionDamjan Marion1-1/+1
Change-Id: I9a0df8d15deefdf31cfead56c96433cd7220b802 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-30Crude stat segment lock recoveryDave Barach1-1/+1
Make sure that vpp_get_stats main heap does not address-collide with the stats segment, which lands "somewhere" in the vpp address space. Add mising MAP_ANONYMOUS flag in clib_mem_vm_map Change-Id: I8a671d174eefd8dd24771ad2ed9f1250e2c7a9f8 Signed-off-by: Dave Barach <dave@barachs.net> Signed-off-by: Ole Troan <ot@cisco.com>
2018-08-30cmake: a bit of packaging workDamjan Marion1-1/+2
Change-Id: I40332c2348c4aab873d726532f2ac3c4abde7ec9 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-2832/64 shmem bihash interoperabilityDave Barach7-37/+363
Move the binary api segment above 4gb Change-Id: I40e8aa7a97722a32397f5a538b5ff8344c50d408 Signed-off-by: Dave Barach <dave@barachs.net>
2018-08-26cmake: add add_vpp_library and add_vpp_executable macrosDamjan Marion1-29/+34
Change-Id: I1382021a6f616571b4b3243ba8c8999239d10815 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-24Rename struct mallinfo -> struct dlmallinfoDave Barach3-10/+10
Also: don't #include /usr/include/malloc.h in dlmalloc.h Change-Id: Ic73ff8862cc8aba371488b912255e28dd96374ff Signed-off-by: Dave Barach <dave@barachs.net>
2018-08-24cmake: fix -DVPP_USE_DLMALLOC=OFFDamjan Marion1-2/+12
Change-Id: Ib8dc37b1a39c92a0c7b22cebdf985c6afa8229d9 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-23bihash: remove unused countersDamjan Marion2-7/+0
Change-Id: I1f0aae16e4ace850d7d79b9c2c644a3e0d002636 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-23clib_mem_is_heap_object() needs to recognize sys_alloc segmentsDave Barach1-0/+4
Preferably without mistaking -pie (address randomized) segment addresses for heap objects. Change-Id: Idca6b966f14b1caf6b4637843fe407dbc5017535 Signed-off-by: Dave Barach <dave@barachs.net>
2018-08-22bihash: add support for reuse of expired entry when bucket is full (VPP-1272)Matus Fabian3-2/+81
Applications such as NAT that dynamically create entries require these entries to expire after some time. Bihash user can now lazily delete expired entries. When inserting and bucket is full, expired entry is overwritten. Change-Id: I6852305df399b546159407f1729c856afde5a634 Signed-off-by: Matus Fabian <matfabia@cisco.com>
2018-08-20Enable storing state in flowhash hash tablesPierre Pfister1-1/+12
Flowhash user can now rely on the table to be initialized to zero and know when an entry is cleaned up by the garbage collector. This is usefull to store state in flowhash entries without the need for callbacks when an entry timeouts. Change-Id: Ieece6b7277241f84ea3f2473d0771c6ee8ce460c Signed-off-by: Pierre Pfister <ppfister@cisco.com>
2018-08-17CMake as an alternative to autotools (experimental)Damjan Marion2-1/+236
Change-Id: Ibc59323e849810531dd0963e85493efad3b86857 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-08fix typo in bitmap.hKorian Edeline1-1/+1
Change-Id: I11587fc382a529cfd9c0971cc2ad59cd97dd6a13 Signed-off-by: Korian Edeline <korian.edeline@ulg.ac.be>
2018-08-06dlmalloc compiles errors with clangNeale Ranns1-1/+5
of the form: /home/nranns/Src/vpp/build-data/../src/vppinfra/dlmalloc.c:4327:7: error: logical not is only applied to the left hand side of this comparison [-Werror,-Wlogical-not-parentheses] if (!(ms)->magic == mparams.magic) { /home/nranns/Src/vpp/build-data/../src/vppinfra/dlmalloc.c:4696:20: error: equality comparison with extraneous parentheses [-Werror,-Wparentheses-equality] if (((ms)->magic == mparams.magic)) { $ lsb_release -a No LSB modules are available. Distributor ID: Ubuntu Description: Ubuntu 16.04.2 LTS Release: 16.04 Codename: xenial $ clang --version clang version 3.8.0-2ubuntu4 (tags/RELEASE_380/final) Target: x86_64-pc-linux-gnu Thread model: posix InstalledDir: /usr/bin Change-Id: If6d70a87420bd54c8e1b8be1d9e9031f6c699c45 Signed-off-by: Neale Ranns <nranns@cisco.com>
2018-08-06fix dangling reference in foreach_key_value_pairDave Barach1-0/+7
When the user deletes the last entry in a bihash bucket, the bihash infra frees the bucket's backing storage. If this happens under clib_bihash_foreach_key_value_pair - and the freed bucket happens to be the bucket being traversed - the resulting dangling reference can easily make the wheels fall off. Simple fix: if (bucket-is-now-empty) double-break. Change-Id: Idc44247a82ed5d0ba548507b4a53d4c8503ba8bb Signed-off-by: Dave Barach <dave@barachs.net>
2018-08-03vlib: avoid double process dispatchFlorin Coras2-0/+6
Change-Id: I46467b1f149be9dfbd00e3ea6d60681d19acf235 Signed-off-by: Florin Coras <fcoras@cisco.com> Signed-off-by: Andrew Yourtchenko <ayourtch@gmail.com>
2018-08-01Improve cpu { coremask-% } configure optionYi He1-0/+36
Accept any sized hexadecimal bitmask specification to support platforms with hundreds of cores. Change-Id: Ib881db0cf60f78bdeffa13acfc2fc7fe7e128cc4 Signed-off-by: Yi He <yi.he@arm.com>
2018-08-01Store USE_DLMALLOC in vppinfra/config.hDamjan Marion3-3/+3
Change-Id: Ib596e7f525b83dc7e830bcf6a126cd210216ce86 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-01Add support for shuffle vector intrinsic via Neon in ARMSirshak Das1-0/+16
This adds byte_swap (variant of shuffle) and shuffle vector intrinsic for ARM based on Neon, concuring with same signature as SSE vector intrinsic. Change-Id: I386fd2b1dcc83654e4ad9f90a6065d7736e4ce5c Signed-off-by: Sirshak Das <sirshak.das@arm.com>
2018-07-31Poison freed memory objectsDave Barach1-0/+8
When compiled w/ -DCLIB_DEBUG=1, paint 0x13 across freed memory blocks. Should result in a characteristic SIGSEGV if someone dereferences a pointer in a freed vector element, etc. Change-Id: I5f78970f4342310bfbe7adeddb56feff21f0de2c Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-31Fix undefined symbol: fformat_append_cr in vat plugins loadingYi He1-0/+11
Several test plugins report undefined symbol while being loaded by load_one_vat_plugin. Fix this by adding VPP_API_TEST_BUILTIN into CFLAGS for building these plugins. Change-Id: I908720fd0d01da1ead30ba17027ba10358f6bdf1 Signed-off-by: Yi He <yi.he@arm.com>
2018-07-28session/dlmalloc: coverity fixesFlorin Coras1-1/+2
Change-Id: I17ffec018f5d2fb06a7a3af6d8bc6128ffee3ae6 Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-07-27dlmalloc: use static magic constant for debug imagesFlorin Coras2-0/+4
Avoids crashes on restarts if svm root region backing file was not cleaned up. Change-Id: I608cf5711aa8c3f9620900473bdf76bde8b918de Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-07-27Fix build-break when compiling -O0 / TAG=vpp_debugDave Barach1-1/+1
Without inlining [TAG=vpp_debug], gcc7 (at least) refuses to produce the indicated vector unit instruction. Change-Id: I0f0400ad74b1e498dce7963a85c47d33afe0a768 Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-27128-bit SIMD version of vlib_get_buffersDamjan Marion1-0/+36
Change-Id: I1a28ddf535c80ecf4ba4bf31659ff2fead1d8a64 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-07-27mips64: Add timer and longjump supportCarl Smith4-6/+92
Also correct types.h for mips64 which could never be hit as _mips was part of the previous ifdef. Change-Id: Id0435c8fc960c5d25c43129b9d9f1606e39ba8e3 Signed-off-by: Carl Smith <carl.smith@alliedtelesis.co.nz>
2018-07-27vector indicies walk in reverseNeale Ranns1-0/+4
Change-Id: Iddc8a940601230f8b209c5601e4e5bd04b103c6a Signed-off-by: Neale Ranns <neale.ranns@cisco.com>
2018-07-27-DCLIB_DEBUG => turn on extra checks in dlmallocDave Barach2-2/+26
Also: call os_panic() on a heap botch crash, attempt to generate a post-mortem API dump, etc. Add an "ugly" test case to vec_test.c, to cause a configurable block overrun. Change-Id: I7b29a7645277f9e485e06ff83335306fedc24b71 Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-26vppinfra: add SSE4.2 version of u8x16_shuffleDamjan Marion1-0/+6
Change-Id: I4bf1cfe5a9492092a7362675079c47629b6f0ee8 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-07-25Generate vppinfra/config.h from config.in script (same as we do for ↵Neale Ranns1-0/+23
vlib/config.h) Change-Id: I55549b589e34a62d3704f788fce801392de22f46 Signed-off-by: Neale Ranns <nranns@cisco.com>
2018-07-20bihash: give hint to CPU that we are spinlockingDamjan Marion2-4/+6
Change-Id: I78c0a6da5d8fc63c1ced43589c42abc15ab12b16 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-07-20Fine-grained add / delete lockingDave Barach9-354/+234
Add a bucket-level lock bit. Use a spinlock only when actually allocating, freeing, or splitting a bucket. Should improve multi-thread add/del performance. Change-Id: I3e40e2a8371685457f340d6584dea14e3207f2b0 Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-19Fix coverity warning / legitimate minor bugDave Barach1-1/+1
Of the form "if ((foo & 0x10) == 1)", as opposed to "if (foo & 0x10)" Change-Id: I6a6d276aeed4af7c1c6c78546ee68d598d54d7db Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-18Add config option to use dlmalloc instead of mheapDave Barach11-8/+7149
Configure w/ --enable-dlmalloc, see .../build-data/platforms/vpp.mk src/vppinfra/dlmalloc.[ch] are slightly modified versions of the well-known Doug Lea malloc. Main advantage: dlmalloc mspaces have no inherent size limit. Change-Id: I19b3f43f3c65bcfb82c1a265a97922d01912446e Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-18vppinfra: increase max bihash arena size to 512GBDamjan Marion2-11/+21
Change-Id: Ic636297df4c03303fdcb176669f0268d80e22123 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-07-16vppinfra: AVX2 interleave functionsDamjan Marion1-3/+14
Change-Id: I8688f700fccd87484da3e202ca3a070cc14eb267 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-07-12Revert "vppinfra: AVX2 blend"Dave Barach1-6/+0
Causes clang validation failures. The patch did not actually pass validation; unfortunately it received a +1 from fd.io JJB - presumably due to a race condition This reverts commit 779c865cc6c7af5bb435d8b3465d80685370edb2. Change-Id: Ica3697f8f90e67d3eae4debc597f27d7d512004a Signed-off-by: Dave Barach <dbarach@cisco.com>
2018-07-12vppinfra: AVX2 blendDamjan Marion1-0/+6
Change-Id: Ie7a64318f10ebb535c98aff4e25cdfc48f60ff33 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-07-09IGMP improvementsNeale Ranns1-0/+21
- Enable/Disable an interface for IGMP - improve logging - refactor common code - no orphaned timers - IGMP state changes in main thread only - Large groups split over multiple state-change reports - SSM range configuration API. - more tests Change-Id: If5674f1044e7e97274a711f47807c9ba689d7b9a Signed-off-by: Neale Ranns <nranns@cisco.com>
2018-07-04Fix clib_bitmap_next_clear() function when no clear bits leftJohn Lo1-0/+3
If the bitmap has no bit clear after the input bit position i, the function will return i even if its bit is set. Fix is to return the next bit just beyond the free bitmap. This can cause IP neighbor scan crash in ip_neighbor_scan() with a debug image. With production image, ip_neighbor_scan() may still function, AFAICT, with extra neighbor delete attempts for entries already deleted, until these entries are reused for new neighbors. Change-Id: If6422ef6f63908ea39651de4ccbd8cb0b294bd69 Signed-off-by: John Lo <loj@cisco.com>
2018-07-03tcp: update snd_una_max for retranmsitsFlorin Coras1-1/+1
Change-Id: I0573d0aff39581bba96e610228a10ae923a8ca06 Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-07-02Add per-numa page allocation info to 'show memory'Damjan Marion2-0/+64
Change-Id: I64e4e3d68c0f3958323f30b12a26cfaafa8bad85 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-06-30bitmap: add nocheck variants for bit opsFlorin Coras2-20/+54
Change-Id: Ifd155e2980a9f8e6af9bb6b08619c15b2bf18ef1 Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-06-29bihash key compare improvementsDamjan Marion3-12/+10
Looks like CPU doesn't like overlaping loads. This new codes in some cases shows 3-4 clock improvements. Change-Id: Ia1b49976ad95140c573f892fdc0a32eebbfa06c8 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-06-28Fix mheap_get_aligned() performance jackpotDave Barach2-3/+64
If non-trivial alignment (e.g. 64) requested, and the object size (e.g. 16) is smaller than (alignment_request - MHEAP_ELT_OVERHEAD_BYTES), round up the size request. This avoids creating remainder chunks, which are false-cache-line-sharing bait to begin with. Change-Id: Ie1a21286d29557d125bb346254b1be2def868b1a Signed-off-by: Dave Barach <dave@barachs.net>
2018-06-28ip: vectorized ip checksumDamjan Marion1-0/+28
Change-Id: Ida678e6f31daa8decb18189da712a350336326e2 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-06-27Tune pool_get / pool_putDave Barach2-7/+56
Stop spending cycles repeatedly tail-trimming the pool free element bitmap; possibly at the expense of slightly hurting pool_foreach peformance. Change-Id: I8a7f3e7b26c71d7496ba9393b2a167dc7f538355 Signed-off-by: Dave Barach <dave@barachs.net>
2018-06-27vppinfra: add vector horizontal add and byte swap (SSE4.2 & AVX2)Damjan Marion2-0/+31
Change-Id: I4e0fd487970796f0153a5b16333827d23b57deac Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-06-26Fix load_unaligned undefined and other possible build failuresSirshak Das1-26/+40
Add aarch64 neon intrinsics to fix build failures similar to this: error: implicit declaration of function ‘u64x2_load_unaligned’ Change-Id: I6178504a48242742df3f7d75abdaf108796cf73f Signed-off-by: Sirshak Das <sirshak.das@arm.com>
2018-06-26We don't have (yet) 128-bit unaligned load/store on ARMDamjan Marion1-2/+2
Change-Id: I16395bbf843e338cdd366d85bb4df3de95d9b265 Signed-off-by: Damjan Marion <damarion@cisco.com>