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2018-02-06Provide page-aligned length to ftruncate.Igor Mikhailov (imichail)1-1/+1
For some files such as hugepages files, ftruncate() fails with the error "Invalid argument" if the 'length' parameter is not on a page boundary. Change-Id: I42a9cde98707da15e3c5d1653046e2277fc7a424 Signed-off-by: Igor Mikhailov (imichail) <imichail@cisco.com>
2018-02-05session: segment manager refactorFlorin Coras1-2/+19
- use valloc as a 'central' segment baseva manager - use per segment manager segment pools and use rwlocks to guard them - add session test that exercises segment creation - embed segment manager properties into application since they're shared - fix rw locks Change-Id: I761164c147275d9e8a926f1eda395e090d231f9a Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-02-01Add flowhash hash table to vppinfraPierre Pfister4-0/+998
This hash table intends to provide an alternative to the widely used bihash table in places where either: - Hash entry timeout is required - The hash table data does not fit in CPU cache Although the bihash table is very fast, each lookup requires accessing two cache lines in a serialized fashion. It works fine when the hash table is in cache, but hits a wall when it does not. The 'flowhash' table uses a simplified design (at the cost of a less good bucket auto-scaling) where each access only requires a single memory lookup (in the absence of collision). The hash table also uses a reduced number of registers. In practice, a VPP node implementing a stateful feature would typically: - prefetch buffer metadata (in-cache) - prefetch packet header (in-cache) - compute hash & prefetch hash bucket (possibly in RAM) - read/write key and value from bucket Using this hash table, it is possible to pipeline accesses in a way that does not exhaust CPU's line field buffers, even when the requested value is located in RAM (i.e. not in cache). Measurements showed it was possible to scale to tens of millions of flows (with a full 5-tuple matching and 32B value, i.e. 1 cache line per flow) with no performance degradation when the hash table grows to the point it doesn't fit in cache anymore. I have used this table in a couple of non-open-sourced projects, but think it might be useful to lb, nat, and possibly other VPP subsystems. More information in the .h file. Change-Id: I2b13dde0eabd868b75da1cedbfca0bf74d705102 Signed-off-by: Pierre Pfister <ppfister@cisco.com>
2018-01-30Compile valloc.c, install header file, etc.Dave Barach1-1/+1
Change-Id: Ibc252d9ed595be955790ec1c97d8730e43ad89b2 Signed-off-by: Dave Barach <dave@barachs.net>
2018-01-30Arm system counter cleanupBrian Brooks2-18/+19
Add some description and cleanup code that uses Arm system counter. Change-Id: Ie1fe00e3e4b5d98867617b7b0184ac526e333c53 Signed-off-by: Brian Brooks <brian.brooks@arm.com>
2018-01-27First-fit virtual space allocatorDave Barach3-0/+700
Change-Id: I75e6c7d1a6ff1fcebc81ec10bd86b79f2bf3dc22 Signed-off-by: Dave Barach <dave@barachs.net>
2018-01-25vppinfra: add readers-writer lockFlorin Coras1-14/+98
Change-Id: I606fd89c410369cbd9ce9dcaaaa9dc58796e7c0e Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-01-25session: add support for memfd segmentsFlorin Coras2-2/+3
- update segment manager and session api to work with both flavors of ssvm segments - added generic ssvm slave/master init and del functions - cleanup/refactor tcp_echo - fixed uses of svm fifo pool as vector Change-Id: Ieee8b163faa407da6e77e657a2322de213a9d2a0 Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-01-24Adding a format function for bihash init routine to format the key, value, ↵Vijayabhaskar Katamreddy2-3/+28
when verbose option is used Change-Id: Ib63ead4525332f897b8a1d8a4cf5a0eb1da1e7f3 Signed-off-by: Vijayabhaskar Katamreddy <vkatamre@cisco.com>
2018-01-19Sub-Interface deletion not cleanup hash's properly (VPP-1136)John Lo1-4/+6
On deleting sub-interfaces, functions vnet_delete_sub_interface() and vnet_delete_hw_interface() are not cleaning up sub-interface related hash tables and memory properly. Change-Id: I17c7c4b2078c062c77bfe48889beb677610035ca Signed-off-by: John Lo <loj@cisco.com> (cherry picked from commit 7f5bec647c9dc743c015d461d040e63a77fd0a08)
2018-01-17ssvm: reuse clib mem infra for memfd segmentsFlorin Coras2-8/+64
Change-Id: I67648dbed3c7ed291b3e1ce617d83a776d3623bb Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-01-09physmem: fix physmem allocation on kernels without NUMA supportDamjan Marion1-4/+4
Change-Id: I056598a1818a39c2da73e252600c14585e5aae83 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-01-09api: refactor vlibmemoryFlorin Coras1-0/+1
- separate client/server code for both memory and socket apis - separate memory api code from generic vlib api code - move unix_shared_memory_fifo to svm and rename to svm_fifo_t - overall declutter Change-Id: I90cdd98ff74d0787d58825b914b0f1eafcfa4dc2 Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-01-06aarch64 - show cpu microarchitectureGabriel Ganne1-0/+50
Combine implementer, part, variant, and revision into one cpu description line. For example : ARM (Cortex-A57 PASS 1.2) * get infos from /proc/cpuinfo * only recognize armv8 processors * add all given cavium processors * Cavium starts counting variants from 1 instead of 0 Change-Id: I4f3820fb13a6bd2a0dc59e28fbe6f48a5b0ceb25 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2018-01-05sock api: add infra for bootstrapping shm clientsFlorin Coras1-0/+7
- add function to sock client that bootstraps shm api - allow sock clients to request custom shm ring configs Change-Id: Iabc1dd4f0dc8bbf8ba24de37f4966339fcf86107 Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-01-05Unify and cleanup usage of hash_set/unset_mem by various tunnelsJohn Lo1-0/+21
Move the functions hash_set_key_copy() and hash_unset_key_free() which are dupilicated in various tunnel support code modules to hash.h as hash_set_mem_alloc() and hash_unset_mem_free() to be used by all. Change-Id: I40723cabe29072ab7feb1804c221f28606d8e4fe Signed-off-by: John Lo <loj@cisco.com>
2017-12-16Use crc32 wrapper (VPP-1086)Gabriel Ganne2-2/+7
This allows arm platforms to also take advantage of crc32 hardware acceleration. * add a wrapper for crc32_u64. It's the only one really used. Using it instead of a call to clib_crc32c() eases building symmetrical hash functions. * replace #ifdef on SSE4 by a test on clib_crc32c_uses_intrinsics. Note: keep the test on i386 * fix typo in lb test log Change-Id: I03a0897b70f6c1717e6901d93cf0fe024d5facb5 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-12-15implement clib_smp_pause() for arm and aarch64 platformKevin Wang2-1/+4
Change-Id: Ic9c1c70e06b953538ed43fc91ed26b6be82ce812 Signed-off-by: Kevin Wang <kevin.wang@arm.com>
2017-12-14vppinfra: add AVX512 variant of clib_memcpyDamjan Marion4-129/+357
Taken from DPDK, also AVX2 variant updated to be in sync with DPDK version. Change-Id: I8a42e4141a5a1a8cfbee328b07bd0c9b38a9eb05 Signed-off-by: Damjan Marion <damarion@cisco.com>
2017-12-14VPP-1032: clean up coverity warnings.Dave Barach2-5/+12
"This time, for sure..." Change-Id: Ie981003842d37c5eb6a0b2fe3abe974a93b86df8 Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-13VPP-1032: fix coverity warningsDave Barach1-1/+2
Change-Id: Ic551af286aa84293deb260560c12def430449598 Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-12Add chi-squared test statistic calculator to random.cDave Barach3-1/+108
Change-Id: I0a0f8c9aad1530d18c70c962e729e84948a074ee Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-08vppinfra: fix issues depending on compilerSergio Gonzalez Monroy1-34/+34
It looks like different compiler versions produce different results for expressions like "(cast) ptr + inc". Use parenthesis to avoid such issues. Change-Id: I93a9883bf5fc05ae462df5b004817775f0739405 Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
2017-12-06UT: Repaired broken C unit tests (--enable-tests)Ole Troan2-2/+2
Change-Id: I63d720378b92813993525f80fee90fc79df27fba Signed-off-by: Ole Troan <ot@cisco.com>
2017-12-06Remove unused, uninteresting codeDave Barach4-1124/+0
Move elog_sample.c to src/examples/vlib Change-Id: I7d32c83c424b9ca4a057372c7fc6a6e2b7dab034 Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-06make clib_maplog_update_header(...) globally accessibleDave Barach3-22/+56
clib_maplog_process(...): handle logs which weren't closed properly. It will happen. Change-Id: Ibcf9c9ea7a09991e6294050e7d2979a0d3f965cf Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-05fill "show cpu" Flag list on aarch64 platforms (VPP-1065)Gabriel Ganne2-6/+84
use getauxval(AT_HWCAP) to get the processor capabilities. The result should be the same as calling cat /proc/cpuinfo | grep Feature | head -n1 All but one (aes) features have a different name. handle aes by adding it an arch prefix, which is skipped during print and a clib_cpu_supports_aes() custom function. Change-Id: If9830bd5a17bac1bd1b5337dacbb0ddbb8ed6b18 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-12-05remove smp dead code (VPP-1066)Gabriel Ganne3-729/+0
this follows commit 01d86c7f6f05938c7d3fe181bd0aa2f75ccdd1df which removed many unused functions from smp.h Change-Id: I3aa0954a5e2319cc526fa68dda113f3cbe063960 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-12-02maplog headers, offline processing, doxygen tagsDave Barach3-30/+384
Change-Id: I0545018ec02f3706ad6a2da6fc13537db5c31a2d Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-01Coverity warning be goneDave Barach1-1/+1
Change-Id: I0946c0a124f3fc9a0aa87499a35edfeaabaec932 Signed-off-by: Dave Barach <dave@barachs.net>
2017-11-30mmap-based fixed-size record double-buffered loggerDave Barach3-0/+357
Change-Id: I760b482b9de457bbb17de817db7079b57d3f5ec1 Signed-off-by: Dave Barach <dave@barachs.net>
2017-11-22use intel intrinsics in clib_memcpy64_x4Damjan Marion1-47/+54
While my original attmept was to write this function to be portable and work on non-x86 systems, seems that gcc-5 desn't respect aligment attribute and issues alligned vector insutruciton which causes crash. Change-Id: If165c8d482ac96f2b71959d326f9772b48097b48 Signed-off-by: Damjan Marion <damarion@cisco.com>
2017-11-21use REV on aarch64 for endianness swapping (VPP-1067)Gabriel Ganne1-0/+19
Change-Id: I2de52725f40380422ca5019405df36cc05681603 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-11-18Call a plugin init function by nameDave Barach1-0/+3
Use this macro to arrange init function ordering between friend plugins. Fails in the usual manner if the plugin doesn't exist, or if the init function symbol is AWOL. clib_error_t * thisplug_init (vlib_main_t *vm) { clib_error_t *error = 0; if ((error = vlib_plugin_init_function ("otherplug.so", otherplug_init))) return error; <etc> return error; } VLIB_INIT_FUNCTION(thisplug_init); Change-Id: Ideecaf46bc0b1546e85096e54be8ddef87946565 Signed-off-by: Dave Barach <dave@barachs.net>
2017-11-15armv8 crc32 - fix macro nameGabriel Ganne1-1/+1
Change-Id: Iba2d20c0a3d4f07457d108d014a6fa4522cb8e2c Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-11-14vppinfra: fix pool_get_aligned_will_expand for fixed poolsFlorin Coras1-3/+4
Change-Id: Ia66ac0a2fa23a3d29370b54e2014900838a8d3ac Signed-off-by: Florin Coras <fcoras@cisco.com>
2017-11-13dpdk: introduce AVX512 variants of node functionsDamjan Marion3-0/+77
Change-Id: If581feca0d51d0420c971801aecdf9250c671b36 Signed-off-by: Damjan Marion <damarion@cisco.com>
2017-11-11Update CPU listDamjan Marion1-17/+35
Change-Id: Ibee8973270366c38dced6eb3e8ca41784549183a Signed-off-by: Damjan Marion <damarion@cisco.com>
2017-11-10add warning control macro setGabriel Ganne1-0/+103
Add a way to toggle on and off a warning for a specific section of code. This supports clang and gcc, and has no effect for any other compilers. This follows commit bfc29ba442dbb65599f29fe5aa44c6219ed0d3a8 and provides a generic way to handle warnings in such corner cases. To disable a warning enabled by "-Wsome-warning" for a specific code: WARN_OFF(some-warning) // disable compiler warning ; /* some code */ WARN_ON(some-warning) // enable the warning again Change-Id: I0101caa0aa775e2b905c7b3b5fef3bbdce281673 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-11-10vppinfra: add 512-bit vector definitions and typesDamjan Marion1-0/+25
Change-Id: I245c034684ba8585c8f5bb5353027aba13f8a53e Signed-off-by: Damjan Marion <damarion@cisco.com>
2017-11-09lock initJingLiuZTE1-0/+1
writer_lock must be inited before used. Change-Id: Ib258aa09b3bccc4de6edba0eb75a7eec20f1a61f Signed-off-by: JingLiuZTE <liu.jing5@zte.com.cn>
2017-11-03silence clib_mem_unaligned() invalid read found by address-sanitizerGabriel Ganne1-19/+28
clib_mem_unaligned + zap64 casts its input as u64, computes a mask according to the input length, and returns the casted maked value. Therefore all the 8 Bytes of the u64 are systematically read, and the invalid ones are discarded. Since they are discarded correctly, this invalid read can safely be ignored. Revert "fix clib_mem_unaligned() invalid read" This reverts commit 0ed3d81a5fa274283ae69b69a405c385189897d3. Change-Id: I5cc33ad36063c414085636debe93707d9a75157a Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-11-03vppinfra: make _vec_resize_will_expand read-onlyFlorin Coras1-7/+3
Change-Id: Ibcc20c24f6feb2b91245b0d88830a6c730d704e6 Signed-off-by: Florin Coras <fcoras@cisco.com>
2017-11-01fix clib_mem_unaligned() invalid readGabriel Ganne1-17/+18
clib_mem_unaligned + zap64 casts its input as u64, computes a mask according to the input length, and returns the casted maked value. Therefore all the 8 Bytes of the u64 are systematically read, and the invalid ones are discarded. For example, for a 5-Bytes string, we will do an invalid read of size 3, even though those 3 Bytes are never used. This patch proposes to only read what we have at the cost of reading as a u64 in one call, but that way, we do not trigger an invalid read error. Change-Id: I3e0b31c4113d9c8e53aa5fa3d3d396ec80f06a27 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-10-30Add the bihash_vec8_8 variantDave Barach2-0/+425
This is an all-purpose octet-vector memory hash, intended as a thread-safe replacement for hash_create_mem / hash_create_string. All u8 * key vectors are memorized by the hash table. Change-Id: I22944daea8fda07dde8ba118a6529a6d382491f9 Signed-off-by: Dave Barach <dave@barachs.net>
2017-10-25Do not include x86intrin.h if unavailableGabriel Ganne1-0/+2
This fixes compilations on arm platforms. The call to the function itself was protected, and used clib_xxhash instead. Only the header protection was missing. Change-Id: I9fac252a5732e1a9808cf7de93fa3d5f07bcebe6 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-10-20add cuckoo hashKlement Sekera7-0/+2472
Change-Id: I78215041588014e9e5c3599c60471ced610735bb Signed-off-by: Klement Sekera <ksekera@cisco.com>
2017-10-17VPP-1032: fix coverity warningsDave Barach1-4/+6
Change-Id: Ic3a0c51e5408921051deaf2e50372d9654574b27 Signed-off-by: Dave Barach <dave@barachs.net>
2017-10-15Fix minor issues in clib_spinlock_unlock()Dave Barach1-1/+3
Change-Id: I20ce799c9dd57332c06003b466ee7c36169bce98 Signed-off-by: Dave Barach <dave@barachs.net>
2017-10-14change format_get_indent() to use u32 instead of uwordGabriel Ganne2-2/+3
This follows commit d3c008d108aa2187d1a2afe2833b4de25ca2c2ab by Christophe Fontaine. Change-Id: I0c4df40df44be2ac0ab25817fa050a1f619eca4d Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>