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2018-02-26Added u8x16,u32x4,u64x2 variants of _zero_byte_mask(x) for ARM/NEON ↵Adrian Oanca1-0/+20
platform. VPP-1129 Change-Id: I954acb56d901e42976e71534317f38d7c4359bcf Signed-off-by: Adrian Oanca <adrian.oanca@enea.com>
2018-02-24u8x16_compare_byte_mask - optimize to use 128bit registers as suggested by ↵Adrian Oanca1-24/+9
Nintin Change-Id: I88aabd34ef385d620695ac17ec3fe2f4a5177ada Signed-off-by: Adrian Oanca <adrian.oanca@enea.com>
2018-02-23Add prefetch inlines, update bi-hash doc tagsDave Barach2-12/+90
Change-Id: I2e9d01ccba5288e89b886464436097d3cb7d2d18 Signed-off-by: Dave Barach <dave@barachs.net>
2018-02-22bihash table size perf/scale improvementsDave Barach3-41/+73
Directly allocate and carve cache-line-aligned chunks of virtual memory. To a first approximation, bihash wasn't using clib_mem_free(...). We eliminate mheap object header/trailers, which improves space efficiency. We also eliminate the 4gb bihash table size limit. An 8_8 bihash w/ 100 million random entries uses 3.8 Gbytes. Change-Id: Icf925fdf99bce7d6ac407ac4edd30560b8f04808 Signed-off-by: Dave Barach <dave@barachs.net>
2018-02-21vppinfra: change default cache line size 64 bytesDamjan Marion1-10/+2
This change only affects Aarch64 where previously we were using 128 bytes. Change-Id: I52a3f2f3ff8c06abe8ae3933bc0d7a2a7749dd8a Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-21vppinfra: remove vector_iwmmxt.hDamjan Marion2-126/+0
Change-Id: I71fac34b071a07b4331cb5c900c3b8667c1fc114 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-21add 'is_all_zero(x)' for NEONAdrian Oanca1-0/+24
Change-Id: I5045e0f3ac4698e820b69ad46b96763e404e6fe4 Signed-off-by: Adrian Oanca <adrian.oanca@enea.com>
2018-02-20vppinfra: autogerate vector typedefs and basic inline functionsDamjan Marion5-379/+83
Change-Id: Ie9f611fa6a962b0937245f5cc949571ba11c5604 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-20Reset expired timer vector length after callbackDave Barach1-1/+4
Otherwise, in a "catch-up / multiple tick" case, the code will repeatedly hand previously-processed expired timer handles to the user callback. Change-Id: Idef4f242279ea41cb557bb6cff5984de02a6503d Signed-off-by: Dave Barach <dave@barachs.net>
2018-02-20vppinfra: CLIB_HAVE_VEC128 mandates SSE4.2Damjan Marion2-9/+3
Change-Id: I6511110d0472203498a4f8741781eeeeb4f90844 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-19Use neutral vector code for ethernet_frame_is_taggedDamjan Marion1-0/+25
Also it removes ethernet_frame_is_any_taged implemebntation which seems to be equally costly compared to two invocations of ethernet_frame_is_tagged. Change-Id: If1c95f8267cd34b807ec07e0d675cbd0db2fdf9f Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-18fix format_hexdumpDamjan Marion1-1/+2
Change-Id: I9710be2e722d716e22d989b3417fb49d2db0848a Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-14vppinfra: Remove empty fileMohsin Kazmi1-0/+0
Change-Id: I3908cc112b40d4bb52da18e7c3ac5ae0af455f87 Signed-off-by: Mohsin Kazmi <sykazmi@cisco.com>
2018-02-09GBP pluginNeale Ranns1-0/+0
Group Base Policy (GBP) defines: - endpoints: typically a VM or container that is connected to the virtual switch/router (i.e. to VPP) - endpoint-group: (EPG) a collection of endpoints - policy: rules determining which traffic can pass between EPGs a.k.a a 'contract' Here, policy is implemented via an ACL. EPG classification for transit packets is determined by: - source EPG: from the packet's input interface - destination EPG: from the packet's destination IP address. Change-Id: I7b983844826b5fc3d49e21353ebda9df9b224e25 Signed-off-by: Neale Ranns <neale.ranns@cisco.com>
2018-02-08add CLIB_HAVE_VEC128 with NEON intrinsics (VPP-1127)Gabriel Ganne2-8/+64
Enable CLIB_HAVE_VEC128 if both aarch64 and __ARM_NEON ie. armv8 only, not armv7 Add more neon compare intrinsics wrappers. I only add simple intrinsics wrappers. More complex ones can be added later as they are needed, with performance tests on the corresponding feature to back them up. Remove wrongly added 128bits definitions defined on both armv7 and armv8 without concern for NEON instructions presence. Notable correspondinf code activations: * MHEAP_FLAG_SMALL_OBJECT_CACHE in mheap.c * ip4 fib mtrie leaves access * enable ixge plugin compilation for aarch64 (conf still disables it by default) Change-Id: I99953823627bdff6f222d232c78aa7b655aaf77a Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2018-02-08Minimize bihash memory consumptionDave Barach3-118/+207
Reference-count the number of entries in each bucket. If the reference count goes to zero, free the backing store. Add long-term churn-testing to test_bihash_template.c, thanks to Andrew Yourtchenko for the initial implementation. Change-Id: I4fbd9229cacfaba8027a85cbf87b74afdead6e39 Signed-off-by: Dave Barach <dave@barachs.net>
2018-02-06vlib: epoll on worker threadsDamjan Marion1-0/+25
This patch teaches worer threads to sleep and to be waken up by kernel if there is activity on file desctiptors assigned to that thread. It also adds counters to epoll file descriptors and new debug cli 'show unix file'. Change-Id: Iaf67869f4aa88ff5b0a08982e1c08474013107c4 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-02-06Provide page-aligned length to ftruncate.Igor Mikhailov (imichail)1-1/+1
For some files such as hugepages files, ftruncate() fails with the error "Invalid argument" if the 'length' parameter is not on a page boundary. Change-Id: I42a9cde98707da15e3c5d1653046e2277fc7a424 Signed-off-by: Igor Mikhailov (imichail) <imichail@cisco.com>
2018-02-05session: segment manager refactorFlorin Coras1-2/+19
- use valloc as a 'central' segment baseva manager - use per segment manager segment pools and use rwlocks to guard them - add session test that exercises segment creation - embed segment manager properties into application since they're shared - fix rw locks Change-Id: I761164c147275d9e8a926f1eda395e090d231f9a Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-02-01Add flowhash hash table to vppinfraPierre Pfister4-0/+998
This hash table intends to provide an alternative to the widely used bihash table in places where either: - Hash entry timeout is required - The hash table data does not fit in CPU cache Although the bihash table is very fast, each lookup requires accessing two cache lines in a serialized fashion. It works fine when the hash table is in cache, but hits a wall when it does not. The 'flowhash' table uses a simplified design (at the cost of a less good bucket auto-scaling) where each access only requires a single memory lookup (in the absence of collision). The hash table also uses a reduced number of registers. In practice, a VPP node implementing a stateful feature would typically: - prefetch buffer metadata (in-cache) - prefetch packet header (in-cache) - compute hash & prefetch hash bucket (possibly in RAM) - read/write key and value from bucket Using this hash table, it is possible to pipeline accesses in a way that does not exhaust CPU's line field buffers, even when the requested value is located in RAM (i.e. not in cache). Measurements showed it was possible to scale to tens of millions of flows (with a full 5-tuple matching and 32B value, i.e. 1 cache line per flow) with no performance degradation when the hash table grows to the point it doesn't fit in cache anymore. I have used this table in a couple of non-open-sourced projects, but think it might be useful to lb, nat, and possibly other VPP subsystems. More information in the .h file. Change-Id: I2b13dde0eabd868b75da1cedbfca0bf74d705102 Signed-off-by: Pierre Pfister <ppfister@cisco.com>
2018-01-30Compile valloc.c, install header file, etc.Dave Barach1-1/+1
Change-Id: Ibc252d9ed595be955790ec1c97d8730e43ad89b2 Signed-off-by: Dave Barach <dave@barachs.net>
2018-01-30Arm system counter cleanupBrian Brooks2-18/+19
Add some description and cleanup code that uses Arm system counter. Change-Id: Ie1fe00e3e4b5d98867617b7b0184ac526e333c53 Signed-off-by: Brian Brooks <brian.brooks@arm.com>
2018-01-27First-fit virtual space allocatorDave Barach3-0/+700
Change-Id: I75e6c7d1a6ff1fcebc81ec10bd86b79f2bf3dc22 Signed-off-by: Dave Barach <dave@barachs.net>
2018-01-25vppinfra: add readers-writer lockFlorin Coras1-14/+98
Change-Id: I606fd89c410369cbd9ce9dcaaaa9dc58796e7c0e Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-01-25session: add support for memfd segmentsFlorin Coras2-2/+3
- update segment manager and session api to work with both flavors of ssvm segments - added generic ssvm slave/master init and del functions - cleanup/refactor tcp_echo - fixed uses of svm fifo pool as vector Change-Id: Ieee8b163faa407da6e77e657a2322de213a9d2a0 Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-01-24Adding a format function for bihash init routine to format the key, value, ↵Vijayabhaskar Katamreddy2-3/+28
when verbose option is used Change-Id: Ib63ead4525332f897b8a1d8a4cf5a0eb1da1e7f3 Signed-off-by: Vijayabhaskar Katamreddy <vkatamre@cisco.com>
2018-01-19Sub-Interface deletion not cleanup hash's properly (VPP-1136)John Lo1-4/+6
On deleting sub-interfaces, functions vnet_delete_sub_interface() and vnet_delete_hw_interface() are not cleaning up sub-interface related hash tables and memory properly. Change-Id: I17c7c4b2078c062c77bfe48889beb677610035ca Signed-off-by: John Lo <loj@cisco.com> (cherry picked from commit 7f5bec647c9dc743c015d461d040e63a77fd0a08)
2018-01-17ssvm: reuse clib mem infra for memfd segmentsFlorin Coras2-8/+64
Change-Id: I67648dbed3c7ed291b3e1ce617d83a776d3623bb Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-01-09physmem: fix physmem allocation on kernels without NUMA supportDamjan Marion1-4/+4
Change-Id: I056598a1818a39c2da73e252600c14585e5aae83 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-01-09api: refactor vlibmemoryFlorin Coras1-0/+1
- separate client/server code for both memory and socket apis - separate memory api code from generic vlib api code - move unix_shared_memory_fifo to svm and rename to svm_fifo_t - overall declutter Change-Id: I90cdd98ff74d0787d58825b914b0f1eafcfa4dc2 Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-01-06aarch64 - show cpu microarchitectureGabriel Ganne1-0/+50
Combine implementer, part, variant, and revision into one cpu description line. For example : ARM (Cortex-A57 PASS 1.2) * get infos from /proc/cpuinfo * only recognize armv8 processors * add all given cavium processors * Cavium starts counting variants from 1 instead of 0 Change-Id: I4f3820fb13a6bd2a0dc59e28fbe6f48a5b0ceb25 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2018-01-05sock api: add infra for bootstrapping shm clientsFlorin Coras1-0/+7
- add function to sock client that bootstraps shm api - allow sock clients to request custom shm ring configs Change-Id: Iabc1dd4f0dc8bbf8ba24de37f4966339fcf86107 Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-01-05Unify and cleanup usage of hash_set/unset_mem by various tunnelsJohn Lo1-0/+21
Move the functions hash_set_key_copy() and hash_unset_key_free() which are dupilicated in various tunnel support code modules to hash.h as hash_set_mem_alloc() and hash_unset_mem_free() to be used by all. Change-Id: I40723cabe29072ab7feb1804c221f28606d8e4fe Signed-off-by: John Lo <loj@cisco.com>
2017-12-16Use crc32 wrapper (VPP-1086)Gabriel Ganne2-2/+7
This allows arm platforms to also take advantage of crc32 hardware acceleration. * add a wrapper for crc32_u64. It's the only one really used. Using it instead of a call to clib_crc32c() eases building symmetrical hash functions. * replace #ifdef on SSE4 by a test on clib_crc32c_uses_intrinsics. Note: keep the test on i386 * fix typo in lb test log Change-Id: I03a0897b70f6c1717e6901d93cf0fe024d5facb5 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-12-15implement clib_smp_pause() for arm and aarch64 platformKevin Wang2-1/+4
Change-Id: Ic9c1c70e06b953538ed43fc91ed26b6be82ce812 Signed-off-by: Kevin Wang <kevin.wang@arm.com>
2017-12-14vppinfra: add AVX512 variant of clib_memcpyDamjan Marion4-129/+357
Taken from DPDK, also AVX2 variant updated to be in sync with DPDK version. Change-Id: I8a42e4141a5a1a8cfbee328b07bd0c9b38a9eb05 Signed-off-by: Damjan Marion <damarion@cisco.com>
2017-12-14VPP-1032: clean up coverity warnings.Dave Barach2-5/+12
"This time, for sure..." Change-Id: Ie981003842d37c5eb6a0b2fe3abe974a93b86df8 Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-13VPP-1032: fix coverity warningsDave Barach1-1/+2
Change-Id: Ic551af286aa84293deb260560c12def430449598 Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-12Add chi-squared test statistic calculator to random.cDave Barach3-1/+108
Change-Id: I0a0f8c9aad1530d18c70c962e729e84948a074ee Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-08vppinfra: fix issues depending on compilerSergio Gonzalez Monroy1-34/+34
It looks like different compiler versions produce different results for expressions like "(cast) ptr + inc". Use parenthesis to avoid such issues. Change-Id: I93a9883bf5fc05ae462df5b004817775f0739405 Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
2017-12-06UT: Repaired broken C unit tests (--enable-tests)Ole Troan2-2/+2
Change-Id: I63d720378b92813993525f80fee90fc79df27fba Signed-off-by: Ole Troan <ot@cisco.com>
2017-12-06Remove unused, uninteresting codeDave Barach4-1124/+0
Move elog_sample.c to src/examples/vlib Change-Id: I7d32c83c424b9ca4a057372c7fc6a6e2b7dab034 Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-06make clib_maplog_update_header(...) globally accessibleDave Barach3-22/+56
clib_maplog_process(...): handle logs which weren't closed properly. It will happen. Change-Id: Ibcf9c9ea7a09991e6294050e7d2979a0d3f965cf Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-05fill "show cpu" Flag list on aarch64 platforms (VPP-1065)Gabriel Ganne2-6/+84
use getauxval(AT_HWCAP) to get the processor capabilities. The result should be the same as calling cat /proc/cpuinfo | grep Feature | head -n1 All but one (aes) features have a different name. handle aes by adding it an arch prefix, which is skipped during print and a clib_cpu_supports_aes() custom function. Change-Id: If9830bd5a17bac1bd1b5337dacbb0ddbb8ed6b18 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-12-05remove smp dead code (VPP-1066)Gabriel Ganne3-729/+0
this follows commit 01d86c7f6f05938c7d3fe181bd0aa2f75ccdd1df which removed many unused functions from smp.h Change-Id: I3aa0954a5e2319cc526fa68dda113f3cbe063960 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>
2017-12-02maplog headers, offline processing, doxygen tagsDave Barach3-30/+384
Change-Id: I0545018ec02f3706ad6a2da6fc13537db5c31a2d Signed-off-by: Dave Barach <dave@barachs.net>
2017-12-01Coverity warning be goneDave Barach1-1/+1
Change-Id: I0946c0a124f3fc9a0aa87499a35edfeaabaec932 Signed-off-by: Dave Barach <dave@barachs.net>
2017-11-30mmap-based fixed-size record double-buffered loggerDave Barach3-0/+357
Change-Id: I760b482b9de457bbb17de817db7079b57d3f5ec1 Signed-off-by: Dave Barach <dave@barachs.net>
2017-11-22use intel intrinsics in clib_memcpy64_x4Damjan Marion1-47/+54
While my original attmept was to write this function to be portable and work on non-x86 systems, seems that gcc-5 desn't respect aligment attribute and issues alligned vector insutruciton which causes crash. Change-Id: If165c8d482ac96f2b71959d326f9772b48097b48 Signed-off-by: Damjan Marion <damarion@cisco.com>
2017-11-21use REV on aarch64 for endianness swapping (VPP-1067)Gabriel Ganne1-0/+19
Change-Id: I2de52725f40380422ca5019405df36cc05681603 Signed-off-by: Gabriel Ganne <gabriel.ganne@enea.com>