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2018-10-02VPP-1440: clean up coverity warningsDave Barach1-3/+10
Change-Id: Ic6823fb617ecae547a5f0e28b1e037848e40f682 Signed-off-by: Dave Barach <dave@barachs.net>
2018-10-01Support dynamic dual/quad loop selection on aarch64Lijian Zhang2-0/+95
Currently, there are three variants available on aarch64, qdf24xx, thunderx2t99, and cortex-a72. -DCLIB_N_PREFETCHES is passed to source code to select dual/quad implementation. Besides, different compiler options are applied on these critical functions. gcc-7.3.0 reports ICE(internal compiler error) with -mtune=thunderx2t99, so -mtune=thunderx2t99 is enabled only when gcc version is greater than 7.3.0 Cavium ThunderX2, Impermenter 0x43, Part 0x0af -march=armv8-a+crc+crypto -mtune=thunderx2t99 Qualcomm Centriq 2400, Impermenter 0x51, Part 0xc00 -march=armv8.1-a+crc+crypto -mtune=qdf24xx Cortex-A72, Impermenter 0x41, Part 0xd08 -march=armv8-a+crc+crypto -mtune=cortex-a72 Change-Id: Id5649c6325c1e642d0fd42535e3908793b13e02a Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com> Reviewed-by: Sirshak Das <sirshak.das@arm.com> Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
2018-09-27Trivial: Cleanup some typos.Paul Vinciguerra20-37/+37
This is a new commit for code under a different maintainer. Change-Id: I79fa403fec6a312238a9a4b18b35dbcafaa05439 Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com>
2018-09-24svm: march svm_fifo take 2Florin Coras1-0/+29
Change-Id: Ifa4fceef7edbe43d444790a624957db0817064de Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-09-20bihash template: avoid memory leak upon rehashAndrew Yourtchenko1-0/+3
Call the BV (value_free) when we have performed the rehash and thus no longer need the memory that old value for the bucket refers to. Change-Id: Ibb82174fc8002aeb3e1a6c8d1f90293d73bc45d8 Signed-off-by: Andrew Yourtchenko <ayourtch@gmail.com>
2018-09-19bihash template: reinstate the check for the available memory in the arenaAndrew Yourtchenko2-3/+3
ffb14b9554afa1e58c3657e0c91dda3135008274 has changed the semantics of alloc_arena_next to become an offset off alloc_arena, but in the available memory check in BV (alloc_aligned) it still treats it as a virtual address, resulting in the check always succeeding, thus over a prolonged period bihash arena allocator potentially overwriting whatever is following the arena. Change-Id: I18882c5f340ca767a389e15cca2696a0a97ef015 Signed-off-by: Andrew Yourtchenko <ayourtch@gmail.com>
2018-09-19socket api: do not delay sending of messagesFlorin Coras1-0/+7
Instead of relying on main epoll loop to send messages, try to send as soon as possible. Change-Id: I27c0b4076f3599ad6e968df4746881a6717d4299 Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-09-13vppinfra: optmize clib_count_equal functionsDamjan Marion1-60/+136
Change-Id: Ia4c79d560bfa1118d4683a89a1209a08c5f546b3 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-09-12Add and enable u32x4_extend_to_u64x2_high for aarch64 NEON intrinsics.Sirshak Das1-0/+6
This is the high version of extendto. This function accomplishes the same task as both shuffling and extending done by SSE intrinsics. This enables the NEON version for buffer indexes to buffer pointer translation. Change-Id: I52d7bbf3d76ba69c9acb0e518ff4bc6abf3bbbd4 Signed-off-by: Sirshak Das <sirshak.das@arm.com> Reviewed-by: Steve Capper <steve.capper@arm.com> Reviewed-by: Yi He <yi.he@arm.com> Verified-by: Lijian Zhang <lijian.zhang@arm.com>
2018-09-11bihash 32/64 bit shared memory interopDave Barach2-39/+39
This patch makes 32/64 bit interoperable shared memory bihash tables work regardless of where they're mapped. Change-Id: If5b4a37ccdaa75410eba755c7d7195633de1b30b Signed-off-by: Dave Barach <dave@barachs.net>
2018-09-11Replacing vtbl NEON intrinsic with rev NEON intrinsic for byte_swap.Sirshak Das1-5/+1
Using rev16 vector intrinsic to reverse byteorder in each word independently. Change-Id: I071c40780baffe0bda614ec5d9dd92858f574b0d Signed-off-by: Sirshak Das <sirshak.das@arm.com> Reviewed-by: Steve Capper <steve.capper@arm.com> Reviewed-by: Brian Brooks <brian.brooks@arm.com> Reviewed-by: Yi He <yi.he@arm.com> Verified-by: Lijian Zhang <lijian.zhang@arm.com>
2018-09-11Add u32x4_extend_to_u64x2 for aarch64 using NEON intrinsicsSirshak Das1-0/+6
This is used in vlib_get_buffers_with_offset. Change-Id: If4ff776bc97d21a22e870300b164eeb6a5ec3638 Signed-off-by: Sirshak Das <sirshak.das@arm.com> Reviewed-by: Steve Capper <steve.capper@arm.com> Reviewed-by: Brian Brooks <brian.brooks@arm.com> Reviewed-by: Yi He <yi.he@arm.com> Verified-by: Lijian Zhang <lijian.zhang@arm.com>
2018-09-11Add horizontal add (hadd) vector intrinsic via NEON.Sirshak Das1-0/+6
Having the NEON equivalent of u32x4_hadd for CLIB_HAVE_VEC128 Change-Id: I210f96f7ecb9b80b4753311a68e5e09ccda7e95b Signed-off-by: Sirshak Das <sirshak.das@arm.com> Reviewed-by: Steve Capper <steve.capper@arm.com> Reviewed-by: Brian Brooks <brian.brooks@arm.com> Reviewed-by: Yi He <yi.he@arm.com> Verified-by: Lijian Zhang <lijian.zhang@arm.com>
2018-09-07Improve NTP / kernel time change event handlingDave Barach1-0/+20
clib_time_verify_frequency(...) rejects clock frequency changes greater than 1%. vlib_worker_thread_barrier_sync_int (...) continuously checks that the barrier hold-down timer is not unreasonably far in the future. Change-Id: I00ecb4c20e44de5d6a9c1499fa933e3dd834d11a Signed-off-by: Dave Barach <dbarach@cisco.com>
2018-09-07Remove qsort.c from vppinfraDamjan Marion1-1/+0
Change-Id: Ifcc2717efd242ae2016563d6f3e5cd57fe161e00 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-09-03Compile vppinfra on macOSDamjan Marion25-98/+187
Add missing calls to clib_mem_init to vppinfra test codes. Change-Id: I53ffc6fc287d1a378065bb86c18b6e995ecdb775 Signed-off-by: Damjan Marion <damarion@cisco.com> Signed-off-by: Dave Barach <dave@barachs.net>
2018-09-02cmake: cache line size detectionDamjan Marion1-1/+1
Change-Id: I9a0df8d15deefdf31cfead56c96433cd7220b802 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-30Crude stat segment lock recoveryDave Barach1-1/+1
Make sure that vpp_get_stats main heap does not address-collide with the stats segment, which lands "somewhere" in the vpp address space. Add mising MAP_ANONYMOUS flag in clib_mem_vm_map Change-Id: I8a671d174eefd8dd24771ad2ed9f1250e2c7a9f8 Signed-off-by: Dave Barach <dave@barachs.net> Signed-off-by: Ole Troan <ot@cisco.com>
2018-08-30cmake: a bit of packaging workDamjan Marion1-1/+2
Change-Id: I40332c2348c4aab873d726532f2ac3c4abde7ec9 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-2832/64 shmem bihash interoperabilityDave Barach7-37/+363
Move the binary api segment above 4gb Change-Id: I40e8aa7a97722a32397f5a538b5ff8344c50d408 Signed-off-by: Dave Barach <dave@barachs.net>
2018-08-26cmake: add add_vpp_library and add_vpp_executable macrosDamjan Marion1-29/+34
Change-Id: I1382021a6f616571b4b3243ba8c8999239d10815 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-24Rename struct mallinfo -> struct dlmallinfoDave Barach3-10/+10
Also: don't #include /usr/include/malloc.h in dlmalloc.h Change-Id: Ic73ff8862cc8aba371488b912255e28dd96374ff Signed-off-by: Dave Barach <dave@barachs.net>
2018-08-24cmake: fix -DVPP_USE_DLMALLOC=OFFDamjan Marion1-2/+12
Change-Id: Ib8dc37b1a39c92a0c7b22cebdf985c6afa8229d9 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-23bihash: remove unused countersDamjan Marion2-7/+0
Change-Id: I1f0aae16e4ace850d7d79b9c2c644a3e0d002636 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-23clib_mem_is_heap_object() needs to recognize sys_alloc segmentsDave Barach1-0/+4
Preferably without mistaking -pie (address randomized) segment addresses for heap objects. Change-Id: Idca6b966f14b1caf6b4637843fe407dbc5017535 Signed-off-by: Dave Barach <dave@barachs.net>
2018-08-22bihash: add support for reuse of expired entry when bucket is full (VPP-1272)Matus Fabian3-2/+81
Applications such as NAT that dynamically create entries require these entries to expire after some time. Bihash user can now lazily delete expired entries. When inserting and bucket is full, expired entry is overwritten. Change-Id: I6852305df399b546159407f1729c856afde5a634 Signed-off-by: Matus Fabian <matfabia@cisco.com>
2018-08-20Enable storing state in flowhash hash tablesPierre Pfister1-1/+12
Flowhash user can now rely on the table to be initialized to zero and know when an entry is cleaned up by the garbage collector. This is usefull to store state in flowhash entries without the need for callbacks when an entry timeouts. Change-Id: Ieece6b7277241f84ea3f2473d0771c6ee8ce460c Signed-off-by: Pierre Pfister <ppfister@cisco.com>
2018-08-17CMake as an alternative to autotools (experimental)Damjan Marion2-1/+236
Change-Id: Ibc59323e849810531dd0963e85493efad3b86857 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-08fix typo in bitmap.hKorian Edeline1-1/+1
Change-Id: I11587fc382a529cfd9c0971cc2ad59cd97dd6a13 Signed-off-by: Korian Edeline <korian.edeline@ulg.ac.be>
2018-08-06dlmalloc compiles errors with clangNeale Ranns1-1/+5
of the form: /home/nranns/Src/vpp/build-data/../src/vppinfra/dlmalloc.c:4327:7: error: logical not is only applied to the left hand side of this comparison [-Werror,-Wlogical-not-parentheses] if (!(ms)->magic == mparams.magic) { /home/nranns/Src/vpp/build-data/../src/vppinfra/dlmalloc.c:4696:20: error: equality comparison with extraneous parentheses [-Werror,-Wparentheses-equality] if (((ms)->magic == mparams.magic)) { $ lsb_release -a No LSB modules are available. Distributor ID: Ubuntu Description: Ubuntu 16.04.2 LTS Release: 16.04 Codename: xenial $ clang --version clang version 3.8.0-2ubuntu4 (tags/RELEASE_380/final) Target: x86_64-pc-linux-gnu Thread model: posix InstalledDir: /usr/bin Change-Id: If6d70a87420bd54c8e1b8be1d9e9031f6c699c45 Signed-off-by: Neale Ranns <nranns@cisco.com>
2018-08-06fix dangling reference in foreach_key_value_pairDave Barach1-0/+7
When the user deletes the last entry in a bihash bucket, the bihash infra frees the bucket's backing storage. If this happens under clib_bihash_foreach_key_value_pair - and the freed bucket happens to be the bucket being traversed - the resulting dangling reference can easily make the wheels fall off. Simple fix: if (bucket-is-now-empty) double-break. Change-Id: Idc44247a82ed5d0ba548507b4a53d4c8503ba8bb Signed-off-by: Dave Barach <dave@barachs.net>
2018-08-03vlib: avoid double process dispatchFlorin Coras2-0/+6
Change-Id: I46467b1f149be9dfbd00e3ea6d60681d19acf235 Signed-off-by: Florin Coras <fcoras@cisco.com> Signed-off-by: Andrew Yourtchenko <ayourtch@gmail.com>
2018-08-01Improve cpu { coremask-% } configure optionYi He1-0/+36
Accept any sized hexadecimal bitmask specification to support platforms with hundreds of cores. Change-Id: Ib881db0cf60f78bdeffa13acfc2fc7fe7e128cc4 Signed-off-by: Yi He <yi.he@arm.com>
2018-08-01Store USE_DLMALLOC in vppinfra/config.hDamjan Marion3-3/+3
Change-Id: Ib596e7f525b83dc7e830bcf6a126cd210216ce86 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-08-01Add support for shuffle vector intrinsic via Neon in ARMSirshak Das1-0/+16
This adds byte_swap (variant of shuffle) and shuffle vector intrinsic for ARM based on Neon, concuring with same signature as SSE vector intrinsic. Change-Id: I386fd2b1dcc83654e4ad9f90a6065d7736e4ce5c Signed-off-by: Sirshak Das <sirshak.das@arm.com>
2018-07-31Poison freed memory objectsDave Barach1-0/+8
When compiled w/ -DCLIB_DEBUG=1, paint 0x13 across freed memory blocks. Should result in a characteristic SIGSEGV if someone dereferences a pointer in a freed vector element, etc. Change-Id: I5f78970f4342310bfbe7adeddb56feff21f0de2c Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-31Fix undefined symbol: fformat_append_cr in vat plugins loadingYi He1-0/+11
Several test plugins report undefined symbol while being loaded by load_one_vat_plugin. Fix this by adding VPP_API_TEST_BUILTIN into CFLAGS for building these plugins. Change-Id: I908720fd0d01da1ead30ba17027ba10358f6bdf1 Signed-off-by: Yi He <yi.he@arm.com>
2018-07-28session/dlmalloc: coverity fixesFlorin Coras1-1/+2
Change-Id: I17ffec018f5d2fb06a7a3af6d8bc6128ffee3ae6 Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-07-27dlmalloc: use static magic constant for debug imagesFlorin Coras2-0/+4
Avoids crashes on restarts if svm root region backing file was not cleaned up. Change-Id: I608cf5711aa8c3f9620900473bdf76bde8b918de Signed-off-by: Florin Coras <fcoras@cisco.com>
2018-07-27Fix build-break when compiling -O0 / TAG=vpp_debugDave Barach1-1/+1
Without inlining [TAG=vpp_debug], gcc7 (at least) refuses to produce the indicated vector unit instruction. Change-Id: I0f0400ad74b1e498dce7963a85c47d33afe0a768 Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-27128-bit SIMD version of vlib_get_buffersDamjan Marion1-0/+36
Change-Id: I1a28ddf535c80ecf4ba4bf31659ff2fead1d8a64 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-07-27mips64: Add timer and longjump supportCarl Smith4-6/+92
Also correct types.h for mips64 which could never be hit as _mips was part of the previous ifdef. Change-Id: Id0435c8fc960c5d25c43129b9d9f1606e39ba8e3 Signed-off-by: Carl Smith <carl.smith@alliedtelesis.co.nz>
2018-07-27vector indicies walk in reverseNeale Ranns1-0/+4
Change-Id: Iddc8a940601230f8b209c5601e4e5bd04b103c6a Signed-off-by: Neale Ranns <neale.ranns@cisco.com>
2018-07-27-DCLIB_DEBUG => turn on extra checks in dlmallocDave Barach2-2/+26
Also: call os_panic() on a heap botch crash, attempt to generate a post-mortem API dump, etc. Add an "ugly" test case to vec_test.c, to cause a configurable block overrun. Change-Id: I7b29a7645277f9e485e06ff83335306fedc24b71 Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-26vppinfra: add SSE4.2 version of u8x16_shuffleDamjan Marion1-0/+6
Change-Id: I4bf1cfe5a9492092a7362675079c47629b6f0ee8 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-07-25Generate vppinfra/config.h from config.in script (same as we do for ↵Neale Ranns1-0/+23
vlib/config.h) Change-Id: I55549b589e34a62d3704f788fce801392de22f46 Signed-off-by: Neale Ranns <nranns@cisco.com>
2018-07-20bihash: give hint to CPU that we are spinlockingDamjan Marion2-4/+6
Change-Id: I78c0a6da5d8fc63c1ced43589c42abc15ab12b16 Signed-off-by: Damjan Marion <damarion@cisco.com>
2018-07-20Fine-grained add / delete lockingDave Barach9-354/+234
Add a bucket-level lock bit. Use a spinlock only when actually allocating, freeing, or splitting a bucket. Should improve multi-thread add/del performance. Change-Id: I3e40e2a8371685457f340d6584dea14e3207f2b0 Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-19Fix coverity warning / legitimate minor bugDave Barach1-1/+1
Of the form "if ((foo & 0x10) == 1)", as opposed to "if (foo & 0x10)" Change-Id: I6a6d276aeed4af7c1c6c78546ee68d598d54d7db Signed-off-by: Dave Barach <dave@barachs.net>
2018-07-18Add config option to use dlmalloc instead of mheapDave Barach11-8/+7149
Configure w/ --enable-dlmalloc, see .../build-data/platforms/vpp.mk src/vppinfra/dlmalloc.[ch] are slightly modified versions of the well-known Doug Lea malloc. Main advantage: dlmalloc mspaces have no inherent size limit. Change-Id: I19b3f43f3c65bcfb82c1a265a97922d01912446e Signed-off-by: Dave Barach <dave@barachs.net>