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2019-08-02virtio: add the display information in virtio cliChenmin Sun2-2/+2
Type: fix 1. Add option '[gso-enabled]' in cli 'create interface virtio' 2. Add gso information in virtio_show() Change-Id: I4eb58f4421325ef54a6a68c8341b3a6d3d68136a Signed-off-by: Chenmin Sun <chenmin.sun@intel.com>
2019-08-02quic: fix connection move with multiple workersAloys Augustin1-13/+35
Change-Id: Ibd1012c2c1382de442ed294dd9e8a0ec89349fa1 Type: fix Signed-off-by: Aloys Augustin <aloaugus@cisco.com>
2019-08-01interface: fix pcap tx/rx trace cli handlingJohn Lo4-16/+7
Provide default packet_to_capture value. Display interface name correctly for "pcap tx/rx trace status". Type: fix Signed-off-by: John Lo <loj@cisco.com> Change-Id: I7064d0dbea236a9aff68bba7fbaf2c4a73b16c6f Signed-off-by: John Lo <loj@cisco.com>
2019-08-01session: session pool migration notificationFlorin Coras6-0/+43
Type: feature Change-Id: Ia9a5b1a6d85c7f3f2e6db583b33b5b20029a1e88 Signed-off-by: Florin Coras <fcoras@cisco.com>
2019-08-01vppinfra: fix spinlock and rwlock testsFlorin Coras3-15/+15
Type: fix Change-Id: I67b72b5ad03b972198c27bc0d927867f41b0e20b Signed-off-by: Florin Coras <fcoras@cisco.com>
2019-08-01ipsec: Redo the anit-replay check post decryptNeale Ranns2-0/+36
Type: fix Change-Id: I1fa8c5326d6f22cfb8dd40e97d8a22d11a716922 Signed-off-by: Neale Ranns <nranns@cisco.com>
2019-08-01docs: Small fixes and orderingNathan Skrzypczak2-12/+11
* deactivtates the TODOs on doxygen (were empty) * This move punt.md to readthedocs (should be the new place for dev doc ?) * Makes Handoff queue demo plugin a child of dev doc in doxygen Type: fix Change-Id: I1f0476a911b35208212af8dd608bc76160efd22a Signed-off-by: Nathan Skrzypczak <nathan.skrzypczak@gmail.com>
2019-08-01vppinfra: refactor clib_rwlock_t to use single condition variablejaszha032-25/+19
Previous implementation of clib_rwlock_t used two spinlocks: one writer lock, and one to guard the counter for the number of readers. This implementation uses a single condition variable rw_cnt which has the following properties: if a writer has the rwlock, rw_cnt = -1 if the rwlock is free, rw_cnt = 0 otherwise, rw_cnt > 0 and rw_cnt = number of readers rw_cnt will never be less than -1 Benchmarking: The results below are the cycle counts from test_rwlock.c, configured so that for 10000 iterations, 6 reader and 6 writer threads on separate cores are spawned such that each writer thread increments a global counter 10000 times in each iteration. For Taishan, 4 reader and 4 writer threads are spawned in each test. x86 Xeon old rwlock: 12.473e8, 11.655e8, 13.201e8, 11.347e8, 13.182e8 x86 Xeon new rwlock: 5.881e8, 5.796e8, 6.536e8, 5.540e8, 5.890e8 Aarch64 ThX2* old rwlock: 9.263e7, 8.933e7, 9.074e7, 8.979e7, 9.378e7 Aarch64 ThX2* new rwlock: 7.221e7, 8.107e7, 7.515e7, 7.672e7, 7.386e7 A72 old rwlock: 3.268e6, 3.200e6, 3.086e6, 3.176e6, 3.170e6 A72 new rwlock: 1.261e6, 1.288e6, 1.251e6, 1.229e6, 1.234e6 *ThunderX2 used additional gcc options "-march=armv8.1-a+crc+crypto+lse" Type: refactor Change-Id: I7c347d3037b36205ab532cbcb52a374c846eb275 Signed-off-by: Jason Zhang <jason.zhang2@arm.com> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Reviewed-by: Lijian Zhang <Lijian.Zhang@arm.com>
2019-08-01vppinfra: remove unused historical codeDave Barach3-375/+0
"timer.[ch]" used a signal handler to deliver timer callbacks. Without indulging in a set of sigprocmask(...) system calls, it would be unsafe to use the mechanism. Rather than wait for another developer to accidentally open this particular can of worms, best to remove the code. It's nothing more than an attractive nuisance at this point. Type: refactor Signed-off-by: Dave Barach <dave@barachs.net> Change-Id: Ia3e7b00a389c302b466605dff0c1bf3566b8dbbd
2019-08-01vppinfra: make first bihash add thread-safeDave Barach2-7/+25
Type: fix Signed-off-by: Dave Barach <dave@barachs.net> Change-Id: Ie37ff66faba79e3b8f46c7a704137f9ef2acc773
2019-08-01quic: Improve quicly_ctx handling & crypto ctxNathan Skrzypczak2-135/+148
Type: fix Change-Id: I898de67c017c3a45bed123d81041b32b43f749d0 Signed-off-by: Nathan Skrzypczak <nathan.skrzypczak@gmail.com>
2019-08-01ethernet: Fix node ordering on ARP feautre ARCNeale Ranns1-2/+13
Type: fix Fixes: fe2fff37 this improves the tracing for dropped ARP packets Change-Id: Iefd0391e349fc54f1beebda403b2349534b20c48 Signed-off-by: Neale Ranns <nranns@cisco.com>
2019-08-01nat: handoff rewrite & fixes for multi-workerFilip Varga2-60/+163
Type: fix Change-Id: Ib9164d8f6c681e8900e645306f3a2dc0ac0e40a8 Signed-off-by: Filip Varga <filipvarga89@gmail.com>
2019-08-01vppinfra: refactor clib_spinlock_t to use compare and swapjaszha032-2/+13
Tested performance of a CAS implementation (using __atomic_compare_exchange) against a TAS implementation (using __atomic_exchange) using test_spinlock.c and found some performance improvement. Generated assembly for CAS and TAS implementations show that TAS always executes with a load-store dependency, but CAS moves a branch condition between the load and store so that only a load occurs when the lock is free. Benchmarking: The results below are the cycle counts from test_spinlock.c, configured so that for 10000 iterations, 12 threads on separate cores are spawned, each of which increments a global counter 10000 times in each iteration. For A72, 8 threads are spawned in each test. x86 Xeon TAS: 7.333e8, 7.605e8, 7.535e8, 7.485e8, 7.321e8 x86 Xeon CAS: 5.842e8, 5.433e8, 5.389e8, 5.983e8, 5.552e8 Aarch64 ThX2* TAS: 9.852e7, 10.209e7, 9.190e7, 9.600e7, 9.224e7 Aarch64 ThX2* CAS: 7.640e7, 7.486e7, 7.425e7, 7.269e7, 7.534e7 A72 TAS: 7.289e6, 6.963e6, 7.208e6, 6.976e6, 7.200e6 A72 CAS: 1.695e6, 1.608e6, 1.600e6, 1.634e6, 1.746e6 *ThunderX2 used additional gcc options "-march=armv8.1-a+crc+crypto+lse" Type: refactor Change-Id: Ic5cd97991804f6b012707fad1a5d1a6edb96cd3d Signed-off-by: Jason Zhang <jason.zhang2@arm.com> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Reviewed-by: Lijian Zhang <Lijian.Zhang@arm.com>
2019-08-01tcp: honor snd_wnd in fast rxtFlorin Coras1-1/+4
Type:fix Change-Id: I2f4224a53360f533c086ebde6a3056e60431da87 Signed-off-by: Florin Coras <fcoras@cisco.com>
2019-08-01qos: Uninitialised variable (coverity)Neale Ranns1-0/+3
Type: fix Fixes: 83832e7ced8be8b7de394415feaba70c32e3c38d Change-Id: I63130c442f71d1aef0d389ab00bac8092224bec2 Signed-off-by: Neale Ranns <nranns@cisco.com>
2019-08-01vppapigen: revert "implement reversible repr's"Vratko Polak1-34/+15
The previous change seems to affect all CRCs. Type: fix Fixes: b504777e7f1c9728e65b874284b4dfd39359c8a8. Change-Id: I65e27ce22020e5ebc764b5a51b5fc84992ddb40a Signed-off-by: Vratko Polak <vrpolak@cisco.com>
2019-07-31lb: vip and as dump/detail api'sHongjun Ni7-75/+441
- lb_vip_dump/lb_vip_details - get all vip. - lb_as_dump/lb_as_details - get all as list per vip. - adds api unit test. - adds vpp_lb to test framework. Ticket: Type: feature Change-Id: I24be50d62c5234f3535cc840603ddd9df7eb3f07 Signed-off-by: Hongjun Ni <hongjun.ni@intel.com> Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com> Signed-off-by: Hongjun Ni <hongjun.ni@intel.com>
2019-07-31api: add prefix matcher typedefPaul Vinciguerra1-0/+11
There is a need to be able to specifiy whether a prefix in a request is to match exactly or if more specific prefixes are also desired. Todo: Uncomment defaults, once supported in vppapigen. Type: feature Change-Id: I74fdef0e89e3aefda822c7c0a477e22479297a90 Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com>
2019-07-31nat: elog rewrite for multi-worker supportFilip Varga17-142/+340
Type: fix Change-Id: I04f136a04bc022d223e4bcb5c59920bd1f1fd560 Signed-off-by: Filip Varga <filipvarga89@gmail.com>
2019-07-31devices interface tests: vhosst GSO supportSteven Luong10-25/+310
Add gso option in create vhost interface to support gso and checksum offload. Tested with the following startup options in qemu: csum=on,gso=on,guest_csum=on,guest_tso4=on,guest_tso6=on,guest_ufo=on, host_tso4=on,host_tso6=on,host_ufo=on Type: feature Change-Id: I9ba1ee33677a694c4a0dfe66e745b098995902b8 Signed-off-by: Steven Luong <sluong@cisco.com>
2019-07-31qos: Store functionNeale Ranns6-6/+663
Type: feature store: write a QoS value into the buffer meta-data record: Extract a QoS value from a packet header and store it. mark: Make a change to the content of a packet header by writing a stored QoS value Change-Id: I07d1e87dd1ca90d40ac1ae1774fee1b272cab83f Signed-off-by: Neale Ranns <nranns@cisco.com>
2019-07-31vppapigen: implement reversible repr'sPaul Vinciguerra1-15/+34
Type: feature Change-Id: I92757f041cde399229c42e34515ace0fcd37908b Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com>
2019-07-31build: Append build number for cpack packagesYohanPipereau1-31/+32
add_vpp_packaging maccro was circumventing scripts/version causing: 1. build number not being appended to the package 2. invalid package name format (due to cmake cpack module) Change-Id: I2b9a985357a3f3bd501be6db6ca638d4430f4bbb Type: make Fixes: def35a2352c9a54f748d301ffa47a446d25a83e0 Signed-off-by: YohanPipereau <ypiperea@cisco.com>
2019-07-31pg: clarify the text of error messageAndrew Yourtchenko1-1/+1
Enabling capture on pg with the file already existing results in a misleading error message. Fix the text. Change-Id: I1aea49cfeda3b4bfe6ed7b18fd543948a078508a Type: fix Signed-off-by: Andrew Yourtchenko <ayourtch@gmail.com>
2019-07-31vlib: fix format_error_traceDave Barach1-1/+2
Error index calculation is error_code + error_node->error_heap_index. Type: fix Fixes: gerrit 20802 Signed-off-by: Dave Barach <dave@barachs.net> Change-Id: I66cf05a29b3cfd9ef9c5468e399290e862b784af
2019-07-31vppinfra: added performance test for clib_rwlock_t (test_rwlock.c)jaszha032-0/+265
Spawns a uniform number of writer and reader threads across a number of cores where each writer thread increments a global variable a specified number of times, and the reader threads continually poll the global's value until the writers complete. Type: test Change-Id: I979c3734c6d03139d0802bff1846875d226f6fbb Signed-off-by: Jason Zhang <jason.zhang2@arm.com> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Reviewed-by: Lijian Zhang <Lijian.Zhang@arm.com>
2019-07-31vppinfra: refactor test_and_set spinlocks to use clib_spinlock_tjaszha0317-105/+83
Spinlock performance improved when implemented with compare_and_exchange instead of test_and_set. All instances of test_and_set locks were refactored to use clib_spinlock_t when possible. Some locks e.g. ssvm synchronize between processes rather than threads, so they cannot directly use clib_spinlock_t. Type: refactor Change-Id: Ia16b5d4cd49209b2b57b8df6c94615c28b11bb60 Signed-off-by: Jason Zhang <jason.zhang2@arm.com> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Reviewed-by: Lijian Zhang <Lijian.Zhang@arm.com>
2019-07-31vppinfra: added lock performance test for clib_spinlock_t (test_spinlock.c)jaszha032-0/+207
Spawns a uniform number of threads across a number of cores where each thread increments a global variable a specified number of times. Type: test Change-Id: I12b3a37708a199c297d022348d99dbb0e8349a9f Signed-off-by: Jason Zhang <jason.zhang2@arm.com> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Reviewed-by: Lijian Zhang <Lijian.Zhang@arm.com>
2019-07-31vcl: fix epoll chain validationFlorin Coras1-22/+22
Type:fix Change-Id: I91dfe7e0ae2e632022fbf639ca16c93f570849de Signed-off-by: Florin Coras <fcoras@cisco.com>
2019-07-31api papi: add alias for timestamp(datetime)/timedeltaPaul Vinciguerra4-37/+56
Now that we have support for f64: - create explicit types for timestamp(datetime)/timedelta - update log_details to use timestamp and remove redundant string representation. If you need the string representation, in python do str(timestamp). If you prefer the raw f64 value, the client can pass in the _no_type_conversion option. Type: feature Change-Id: I547b5fa7122d2afa12628b7db0192c23babbbae8 Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com>
2019-07-31vppapigen: add endian_string for f64Paul Vinciguerra1-0/+1
Type: fix Change-Id: I35838baea21ead4a3f45d998ff225a513781d7ee Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com>
2019-07-31ip: Ensure reassembly runs before IPSec decrypt.Neale Ranns2-2/+6
Type: fix Change-Id: I01eeedf8d5015b07b9422c65afe78bfe8177c22c Signed-off-by: Neale Ranns <nranns@cisco.com>
2019-07-31fib: Add some path-list flags to its keyNeale Ranns2-1/+11
Type: fix Ticket: 1729 The flags that are permanently set on a path-list should form part of its key in the path-list DB. Otherwise, if shared, they will not behave as expected. Change-Id: I0aa7c7c5d270c97b08014e4a47ddbdcee2358706 Signed-off-by: Neale Ranns <nranns@cisco.com>
2019-07-31fib: fix calls to unformat_fib_pathNeale Ranns5-7/+10
Type: fix Ticket: 1728 Change-Id: I679c2b8c5b0f751c9476db3669ab3f6c26dcdd28 Signed-off-by: Neale Ranns <nranns@cisco.com>
2019-07-31ipsec: Typo in flag nameNeale Ranns1-1/+1
Type: fix Change-Id: I0c9353598d3c9b7ea587ea8a2b6e1faa5454843d Signed-off-by: Neale Ranns <nranns@cisco.com>
2019-07-30quic: fix cert loadingNathan Skrzypczak3-12/+17
Type: fix Change-Id: I29d24c8ec7b8e0613d4fbf5eedc72384326dc284 Signed-off-by: Nathan Skrzypczak <nathan.skrzypczak@gmail.com>
2019-07-30quic: cleanup and refactorisationAloys Augustin7-525/+634
Change-Id: I031a60ac010b55110f32f0a08e19b1156aeda268 Type: refactor Signed-off-by: Aloys Augustin <aloaugus@cisco.com>
2019-07-30vppinfra: refactor use of CLIB_MEMORY_BARRIER ()jaszha037-27/+14
All instances of test_and_set locks used the following sequence to release the locks: CLIB_MEMORY_BARRIER (); p->lock = 0; // p is a generic struct with a TAS lock Use clib_atomic_release to generate more efficient assembly code. Type: refactor Change-Id: Idca3a38b1cf43578108bdd1afe83b6ebc17a4c68 Signed-off-by: Jason Zhang <jason.zhang2@arm.com> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Reviewed-by: Lijian Zhang <Lijian.Zhang@arm.com>
2019-07-30vlib: Fix packet tracingNeale Ranns1-1/+1
Type: fix Fixes: 99536f4 Change-Id: Ica230ec9fa7f6fd36e2754e8b0b9db555460ca55 Signed-off-by: Neale Ranns <nranns@cisco.com>
2019-07-30tap: fix segv when host-if-name is not givenMohsin Kazmi1-8/+10
Type: fix Fixes: c30d87e6139c64eceade54972715b402c625763d Change-Id: I86b606b18ff6a30709b7aff089fd5dd00103bd7f Signed-off-by: Mohsin Kazmi <sykazmi@cisco.com>
2019-07-30vppinfra: conformed spinlocks to use CLIB_PAUSEjaszha036-8/+14
Modified test-and-set spin locks to call CLIB_PAUSE () when spinning for code consistency. Decreases the memory bandwidth consumed. Type: fix Change-Id: I1cca4f87f44f23f257c7a35466cd2e7767072f51 Signed-off-by: Jason Zhang <jason.zhang2@arm.com> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Reviewed-by: Lijian Zhang <Lijian.Zhang@arm.com>
2019-07-29misc: add vnet/pipeline.h exampleDave Barach1-1/+89
To the sample plugin. We should probably suggest that folks use the pipeline.h coding model more often. It's really easy, and these days the performance results are similar to quad-single loop coding. Type: refactor Change-Id: Ie2caa087972737e6d9c31c4ac79355f3d8ced282 Signed-off-by: Dave Barach <dave@barachs.net>
2019-07-29session: fix vpp to app msg generationFlorin Coras3-68/+32
Type:fix Freeing mq messages in vpp (producer), if enqueueing fails, invalidates consumer assumption that messages can be freed without a lock. Change-Id: I748a33b8846597bdad865945d8e899346d482434 Signed-off-by: Florin Coras <fcoras@cisco.com> Signed-off-by: Tal Saiag <tal.saiag@gmail.com>
2019-07-29vcl: fix config parsing of hex valuesFlorin Coras1-24/+23
Type:fix Change-Id: I31f35dd86fb6efb04d4a449f7fc834296baaa043 Signed-off-by: Tal Saiag <tal.saiag@gmail.com> Signed-off-by: Florin Coras <fcoras@cisco.com>
2019-07-29api acl: breakout acl_types.api for reuse by othersPaul Vinciguerra2-79/+101
Type: refactor Change-Id: I40518ccddcb78e58f7e6a098c27d9ec53e5a1146 Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com>
2019-07-28fib: add invalid source type and fix debug logBenoît Ganne3-19/+22
Add the FIB_SOURCE_INVALID fib source type. This allows to spot uninitialized fib source more easily (0 no longer means special) and we can use it as placeholder when no source is present. Use it to fix FIB_ENTRY_DBG() which was accessing the 1st source, even when no sources were present. Type: fix Fixes: 710071bf0e Change-Id: I980b6a6a07616d4a8d6f2db166a1dd335721c74d Signed-off-by: Benoît Ganne <bganne@cisco.com>
2019-07-28api: add vl_api_version_t typePaul Vinciguerra5-0/+47
Type: feature Depends-on: https://gerrit.fd.io/r/20484 Change-Id: Ifc8d7e00d7254db40856a088fdd352d9773f71d5 Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com>
2019-07-28pg: add GSO supportMohsin Kazmi8-13/+126
Type: feature Change-Id: I72676495a85fbecc946aa266a75234cce70c3a5e Signed-off-by: Mohsin Kazmi <sykazmi@cisco.com>
2019-07-28sr: ipv6 segment routing header (srh) updateAhmed Abdelsalam5-1584/+21
SRH has passed WG review in IETF and currently an IESG document. This patch updates the SRH definition to be compliant with IETF. - Change "first_segment" to "last_entry" - Change "reserved" to "tag" Change-Id: I1765c968671655c5646f6de478d1f7196abbc040 Type: fix Signed-off-by: Ahmed Abdelsalam <ahabdels@cisco.com>