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path: root/src/vnet/ipsec/ipsec_if.c
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/*
 * ipsec_if.c : IPSec interface support
 *
 * Copyright (c) 2015 Cisco and/or its affiliates.
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at:
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include <vnet/vnet.h>
#include <vnet/api_errno.h>
#include <vnet/ip/ip.h>

#include <vnet/ipsec/ipsec.h>
#include <vnet/ipsec/esp.h>

void vl_api_rpc_call_main_thread (void *fp, u8 * data, u32 data_length);

static u8 *
format_ipsec_name (u8 * s, va_list * args)
{
  u32 dev_instance = va_arg (*args, u32);
  return format (s, "ipsec%d", dev_instance);
}

static uword
dummy_interface_tx (vlib_main_t * vm,
		    vlib_node_runtime_t * node, vlib_frame_t * frame)
{
  clib_warning ("you shouldn't be here, leaking buffers...");
  return frame->n_vectors;
}

static clib_error_t *
ipsec_admin_up_down_function (vnet_main_t * vnm, u32 hw_if_index, u32 flags)
{
  ipsec_main_t *im = &ipsec_main;
  clib_error_t *err = 0;
  ipsec_tunnel_if_t *t;
  vnet_hw_interface_t *hi;
  ipsec_sa_t *sa;

  hi = vnet_get_hw_interface (vnm, hw_if_index);
  t = pool_elt_at_index (im->tunnel_interfaces, hi->hw_instance);

  if (flags & VNET_SW_INTERFACE_FLAG_ADMIN_UP)
    {
      ASSERT (im->cb.check_support_cb);

      sa = pool_elt_at_index (im->sad, t->input_sa_index);

      err = im->cb.check_support_cb (sa);
      if (err)
	return err;

      if (im->cb.add_del_sa_sess_cb)
	{
	  err = im->cb.add_del_sa_sess_cb (t->input_sa_index, 1);
	  if (err)
	    return err;
	}

      sa = pool_elt_at_index (im->sad, t->output_sa_index);

      err = im->cb.check_support_cb (sa);
      if (err)
	return err;

      if (im->cb.add_del_sa_sess_cb)
	{
	  err = im->cb.add_del_sa_sess_cb (t->output_sa_index, 1);
	  if (err)
	    return err;
	}

      vnet_hw_interface_set_flags (vnm, hw_if_index,
				   VNET_HW_INTERFACE_FLAG_LINK_UP);
    }
  else
    {
      vnet_hw_interface_set_flags (vnm, hw_if_index, 0 /* down */ );

      sa = pool_elt_at_index (im->sad, t->input_sa_index);

      if (im->cb.add_del_sa_sess_cb)
	{
	  err = im->cb.add_del_sa_sess_cb (t->input_sa_index, 0);
	  if (err)
	    return err;
	}

      sa = pool_elt_at_index (im->sad, t->output_sa_index);

      if (im->cb.add_del_sa_sess_cb)
	{
	  err = im->cb.add_del_sa_sess_cb (t->output_sa_index, 0);
	  if (err)
	    return err;
	}
    }

  return /* no error */ 0;
}

/* *INDENT-OFF* */
VNET_DEVICE_CLASS (ipsec_device_class, static) =
{
  .name = "IPSec",
  .format_device_name = format_ipsec_name,
  .format_tx_trace = format_ipsec_if_output_trace,
  .tx_function = dummy_interface_tx,
  .admin_up_down_function = ipsec_admin_up_down_function,
};
/* *INDENT-ON* */

/* *INDENT-OFF* */
VNET_HW_INTERFACE_CLASS (ipsec_hw_class) =
{
  .name = "IPSec",
  .build_rewrite = default_build_rewrite,
  .flags = VNET_HW_INTERFACE_CLASS_FLAG_P2P,
};
/* *INDENT-ON* */

static int
ipsec_add_del_tunnel_if_rpc_callback (ipsec_add_del_tunnel_args_t * a)
{
  vnet_main_t *vnm = vnet_get_main ();
  ASSERT (vlib_get_thread_index () == 0);

  return ipsec_add_del_tunnel_if_internal (vnm, a, NULL);
}

int
ipsec_add_del_tunnel_if (ipsec_add_del_tunnel_args_t * args)
{
  vl_api_rpc_call_main_thread (ipsec_add_del_tunnel_if_rpc_callback,
			       (u8 *) args, sizeof (*args));
  return 0;
}

int
ipsec_add_del_tunnel_if_internal (vnet_main_t * vnm,
				  ipsec_add_del_tunnel_args_t * args,
				  u32 * sw_if_index)
{
  ipsec_tunnel_if_t *t;
  ipsec_main_t *im = &ipsec_main;
  vnet_hw_interface_t *hi = NULL;
  u32 hw_if_index = ~0;
  uword *p;
  ipsec_sa_t *sa;

  u64 key = (u64) args->remote_ip.as_u32 << 32 | (u64) args->remote_spi;
  p = hash_get (im->ipsec_if_pool_index_by_key, key);

  if (args->is_add)
    {
      /* check if same src/dst pair exists */
      if (p)
	return VNET_API_ERROR_INVALID_VALUE;

      pool_get_aligned (im->tunnel_interfaces, t, CLIB_CACHE_LINE_BYTES);
      memset (t, 0, sizeof (*t));

      pool_get (im->sad, sa);
      memset (sa, 0, sizeof (*sa));
      t->input_sa_index = sa - im->sad;
      sa->spi = args->remote_spi;
      sa->tunnel_src_addr.ip4.as_u32 = args->remote_ip.as_u32;
      sa->tunnel_dst_addr.ip4.as_u32 = args->local_ip.as_u32;
      sa->is_tunnel = 1;
      sa->use_esn = args->esn;
      sa->use_anti_replay = args->anti_replay;
      sa->integ_alg = args->integ_alg;
      if (args->remote_integ_key_len <= sizeof (args->remote_integ_key))
	{
	  sa->integ_key_len = args->remote_integ_key_len;
	  clib_memcpy (sa->integ_key, args->remote_integ_key,
		       args->remote_integ_key_len);
	}
      sa->crypto_alg = args->crypto_alg;
      if (args->remote_crypto_key_len <= sizeof (args->remote_crypto_key))
	{
	  sa->crypto_key_len = args->remote_crypto_key_len;
	  clib_memcpy (sa->crypto_key, args->remote_crypto_key,
		       args->remote_crypto_key_len);
	}

      pool_get (im->sad, sa);
      memset (sa, 0, sizeof (*sa));
      t->output_sa_index = sa - im->sad;
      sa->spi = args->local_spi;
      sa->tunnel_src_addr.ip4.as_u32 = args->local_ip.as_u32;
      sa->tunnel_dst_addr.ip4.as_u32 = args->remote_ip.as_u32;
      sa->is_tunnel = 1;
      sa->use_esn = args->esn;
      sa->use_anti_replay = args->anti_replay;
      sa->integ_alg = args->integ_alg;
      if (args->local_integ_key_len <= sizeof (args->local_integ_key))
	{
	  sa->integ_key_len = args->local_integ_key_len;
	  clib_memcpy (sa->integ_key, args->local_integ_key,
		       args->local_integ_key_len);
	}
      sa->crypto_alg = args->crypto_alg;
      if (args->local_crypto_key_len <= sizeof (args->local_crypto_key))
	{
	  sa->crypto_key_len = args->local_crypto_key_len;
	  clib_memcpy (sa->crypto_key, args->local_crypto_key,
		       args->local_crypto_key_len);
	}

      hash_set (im->ipsec_if_pool_index_by_key, key,
		t - im->tunnel_interfaces);

      if (vec_len (im->free_tunnel_if_indices) > 0)
	{
	  hw_if_index =
	    im->free_tunnel_if_indices[vec_len (im->free_tunnel_if_indices) -
				       1];
	  _vec_len (im->free_tunnel_if_indices) -= 1;
	}
      else
	{
	  hw_if_index =
	    vnet_register_interface (vnm, ipsec_device_class.index,
				     t - im->tunnel_interfaces,
				     ipsec_hw_class.index,
				     t - im->tunnel_interfaces);
	}

      hi = vnet_get_hw_interface (vnm, hw_if_index);
      hi->output_node_index = ipsec_if_output_node.index;
      t->hw_if_index = hw_if_index;

      /*1st interface, register protocol */
      if (pool_elts (im->tunnel_interfaces) == 1)
	ip4_register_protocol (IP_PROTOCOL_IPSEC_ESP,
			       ipsec_if_input_node.index);

    }
  else
    {
      vnet_interface_main_t *vim = &vnm->interface_main;

      /* check if exists */
      if (!p)
	return VNET_API_ERROR_INVALID_VALUE;

      t = pool_elt_at_index (im->tunnel_interfaces, p[0]);
      hi = vnet_get_hw_interface (vnm, t->hw_if_index);
      vnet_sw_interface_set_flags (vnm, hi->sw_if_index, 0);	/* admin down */
      vec_add1 (im->free_tunnel_if_indices, t->hw_if_index);

      vnet_interface_counter_lock (vim);
      vlib_zero_combined_counter (vim->combined_sw_if_counters +
				  VNET_INTERFACE_COUNTER_TX, hi->sw_if_index);
      vlib_zero_combined_counter (vim->combined_sw_if_counters +
				  VNET_INTERFACE_COUNTER_RX, hi->sw_if_index);
      vnet_interface_counter_unlock (vim);

      /* delete input and output SA */
      sa = pool_elt_at_index (im->sad, t->input_sa_index);

      pool_put (im->sad, sa);

      sa = pool_elt_at_index (im->sad, t->output_sa_index);

      pool_put (im->sad, sa);

      hash_unset (im->ipsec_if_pool_index_by_key, key);
      pool_put (im->tunnel_interfaces, t);
    }

  if (sw_if_index)
    *sw_if_index = hi->sw_if_index;

  return 0;
}

int
ipsec_add_del_ipsec_gre_tunnel (vnet_main_t * vnm,
				ipsec_add_del_ipsec_gre_tunnel_args_t * args)
{
  ipsec_tunnel_if_t *t = 0;
  ipsec_main_t *im = &ipsec_main;
  uword *p;
  ipsec_sa_t *sa;
  u64 key;
  u32 isa, osa;

  p = hash_get (im->sa_index_by_sa_id, args->local_sa_id);
  if (!p)
    return VNET_API_ERROR_INVALID_VALUE;
  isa = p[0];

  p = hash_get (im->sa_index_by_sa_id, args->remote_sa_id);
  if (!p)
    return VNET_API_ERROR_INVALID_VALUE;
  osa = p[0];
  sa = pool_elt_at_index (im->sad, p[0]);

  if (sa->is_tunnel)
    key = (u64) sa->tunnel_dst_addr.ip4.as_u32 << 32 | (u64) sa->spi;
  else
    key = (u64) args->remote_ip.as_u32 << 32 | (u64) sa->spi;

  p = hash_get (im->ipsec_if_pool_index_by_key, key);

  if (args->is_add)
    {
      /* check if same src/dst pair exists */
      if (p)
	return VNET_API_ERROR_INVALID_VALUE;

      pool_get_aligned (im->tunnel_interfaces, t, CLIB_CACHE_LINE_BYTES);
      memset (t, 0, sizeof (*t));

      t->input_sa_index = isa;
      t->output_sa_index = osa;
      t->hw_if_index = ~0;
      hash_set (im->ipsec_if_pool_index_by_key, key,
		t - im->tunnel_interfaces);

      /*1st interface, register protocol */
      if (pool_elts (im->tunnel_interfaces) == 1)
	ip4_register_protocol (IP_PROTOCOL_IPSEC_ESP,
			       ipsec_if_input_node.index);
    }
  else
    {
      /* check if exists */
      if (!p)
	return VNET_API_ERROR_INVALID_VALUE;

      t = pool_elt_at_index (im->tunnel_interfaces, p[0]);
      hash_unset (im->ipsec_if_pool_index_by_key, key);
      pool_put (im->tunnel_interfaces, t);
    }
  return 0;
}

int
ipsec_set_interface_key (vnet_main_t * vnm, u32 hw_if_index,
			 ipsec_if_set_key_type_t type, u8 alg, u8 * key)
{
  ipsec_main_t *im = &ipsec_main;
  vnet_hw_interface_t *hi;
  ipsec_tunnel_if_t *t;
  ipsec_sa_t *sa;

  hi = vnet_get_hw_interface (vnm, hw_if_index);
  t = pool_elt_at_index (im->tunnel_interfaces, hi->dev_instance);

  if (hi->flags & VNET_HW_INTERFACE_FLAG_LINK_UP)
    return VNET_API_ERROR_SYSCALL_ERROR_1;

  if (type == IPSEC_IF_SET_KEY_TYPE_LOCAL_CRYPTO)
    {
      sa = pool_elt_at_index (im->sad, t->output_sa_index);
      sa->crypto_alg = alg;
      sa->crypto_key_len = vec_len (key);
      clib_memcpy (sa->crypto_key, key, vec_len (key));
    }
  else if (type == IPSEC_IF_SET_KEY_TYPE_LOCAL_INTEG)
    {
      sa = pool_elt_at_index (im->sad, t->output_sa_index);
      sa->integ_alg = alg;
      sa->integ_key_len = vec_len (key);
      clib_memcpy (sa->integ_key, key, vec_len (key));
    }
  else if (type == IPSEC_IF_SET_KEY_TYPE_REMOTE_CRYPTO)
    {
      sa = pool_elt_at_index (im->sad, t->input_sa_index);
      sa->crypto_alg = alg;
      sa->crypto_key_len = vec_len (key);
      clib_memcpy (sa->crypto_key, key, vec_len (key));
    }
  else if (type == IPSEC_IF_SET_KEY_TYPE_REMOTE_INTEG)
    {
      sa = pool_elt_at_index (im->sad, t->input_sa_index);
      sa->integ_alg = alg;
      sa->integ_key_len = vec_len (key);
      clib_memcpy (sa->integ_key, key, vec_len (key));
    }
  else
    return VNET_API_ERROR_INVALID_VALUE;

  return 0;
}


int
ipsec_set_interface_sa (vnet_main_t * vnm, u32 hw_if_index, u32 sa_id,
			u8 is_outbound)
{
  ipsec_main_t *im = &ipsec_main;
  vnet_hw_interface_t *hi;
  ipsec_tunnel_if_t *t;
  ipsec_sa_t *sa, *old_sa;
  u32 sa_index, old_sa_index;
  uword *p;

  hi = vnet_get_hw_interface (vnm, hw_if_index);
  t = pool_elt_at_index (im->tunnel_interfaces, hi->dev_instance);

  sa_index = ipsec_get_sa_index_by_sa_id (sa_id);
  if (sa_index == ~0)
    {
      clib_warning ("SA with ID %u not found", sa_id);
      return VNET_API_ERROR_INVALID_VALUE;
    }

  if (ipsec_is_sa_used (sa_index))
    {
      clib_warning ("SA with ID %u is already in use", sa_id);
      return VNET_API_ERROR_INVALID_VALUE;
    }

  sa = pool_elt_at_index (im->sad, sa_index);
  if (sa->is_tunnel_ip6)
    {
      clib_warning ("IPsec interface not supported with IPv6 endpoints");
      return VNET_API_ERROR_UNIMPLEMENTED;
    }

  if (!is_outbound)
    {
      u64 key;

      old_sa_index = t->input_sa_index;
      old_sa = pool_elt_at_index (im->sad, old_sa_index);

      /* unset old inbound hash entry. packets should stop arriving */
      key =
	(u64) old_sa->tunnel_src_addr.ip4.as_u32 << 32 | (u64) old_sa->spi;
      p = hash_get (im->ipsec_if_pool_index_by_key, key);
      if (p)
	hash_unset (im->ipsec_if_pool_index_by_key, key);

      /* set new inbound SA, then set new hash entry */
      t->input_sa_index = sa_index;
      key = (u64) sa->tunnel_src_addr.ip4.as_u32 << 32 | (u64) sa->spi;
      hash_set (im->ipsec_if_pool_index_by_key, key, hi->dev_instance);
    }
  else
    {
      old_sa_index = t->output_sa_index;
      old_sa = pool_elt_at_index (im->sad, old_sa_index);
      t->output_sa_index = sa_index;
    }

  /* remove sa_id to sa_index mapping on old SA */
  if (ipsec_get_sa_index_by_sa_id (old_sa->id) == old_sa_index)
    hash_unset (im->sa_index_by_sa_id, old_sa->id);

  if (im->cb.add_del_sa_sess_cb)
    {
      clib_error_t *err;

      err = im->cb.add_del_sa_sess_cb (old_sa_index, 0);
      if (err)
	return VNET_API_ERROR_SYSCALL_ERROR_1;
    }

  pool_put (im->sad, old_sa);

  return 0;
}


clib_error_t *
ipsec_tunnel_if_init (vlib_main_t * vm)
{
  ipsec_main_t *im = &ipsec_main;

  im->ipsec_if_pool_index_by_key = hash_create (0, sizeof (uword));

  return 0;
}

VLIB_INIT_FUNCTION (ipsec_tunnel_if_init);


/*
 * fd.io coding-style-patch-verification: ON
 *
 * Local Variables:
 * eval: (c-set-style "gnu")
 * End:
 */
class="mh">0x4950); /* For each TC in units of 1k bytes. */ u32 tx_packet_buffer_thresholds[8]; CLIB_PAD_FROM_TO (0x4970, 0x4980); struct { u32 mmw; u32 config; u32 status; u32 rate_drift; } dcb_tx_rate_scheduler; CLIB_PAD_FROM_TO (0x4990, 0x4a80); u32 tx_dma_control; CLIB_PAD_FROM_TO (0x4a84, 0x4a88); u32 tx_dma_tcp_flags_control[2]; CLIB_PAD_FROM_TO (0x4a90, 0x4b00); u32 pf_mailbox[64]; CLIB_PAD_FROM_TO (0x4c00, 0x5000); /* RX */ u32 checksum_control; CLIB_PAD_FROM_TO (0x5004, 0x5008); u32 rx_filter_control; CLIB_PAD_FROM_TO (0x500c, 0x5010); u32 management_vlan_tag[8]; u32 management_udp_tcp_ports[8]; CLIB_PAD_FROM_TO (0x5050, 0x5078); /* little endian. */ u32 extended_vlan_ether_type; CLIB_PAD_FROM_TO (0x507c, 0x5080); /* [1] store/dma bad packets [8] accept all multicast [9] accept all unicast [10] accept all broadcast. */ u32 filter_control; CLIB_PAD_FROM_TO (0x5084, 0x5088); /* [15:0] vlan ethernet type (0x8100) little endian [28] cfi bit expected [29] drop packets with unexpected cfi bit [30] vlan filter enable. */ u32 vlan_control; CLIB_PAD_FROM_TO (0x508c, 0x5090); /* [1:0] hi bit of ethernet address for 12 bit index into multicast table 0 => 47, 1 => 46, 2 => 45, 3 => 43. [2] enable multicast filter */ u32 multicast_control; CLIB_PAD_FROM_TO (0x5094, 0x5100); u32 fcoe_rx_control; CLIB_PAD_FROM_TO (0x5104, 0x5108); u32 fc_flt_context; CLIB_PAD_FROM_TO (0x510c, 0x5110); u32 fc_filter_control; CLIB_PAD_FROM_TO (0x5114, 0x5120); u32 rx_message_type_lo; CLIB_PAD_FROM_TO (0x5124, 0x5128); /* [15:0] ethernet type (little endian) [18:16] matche pri in vlan tag [19] priority match enable [25:20] virtualization pool [26] pool enable [27] is fcoe [30] ieee 1588 timestamp enable [31] filter enable. (See ethernet_type_queue_select.) */ u32 ethernet_type_queue_filter[8]; CLIB_PAD_FROM_TO (0x5148, 0x5160); /* [7:0] l2 ethernet type and [15:8] l2 ethernet type or */ u32 management_decision_filters1[8]; u32 vf_vm_tx_switch_loopback_enable[2]; u32 rx_time_sync_control; CLIB_PAD_FROM_TO (0x518c, 0x5190); u32 management_ethernet_type_filters[4]; u32 rx_timestamp_attributes_lo; u32 rx_timestamp_hi; u32 rx_timestamp_attributes_hi; CLIB_PAD_FROM_TO (0x51ac, 0x51b0); u32 pf_virtual_control; CLIB_PAD_FROM_TO (0x51b4, 0x51d8); u32 fc_offset_parameter; CLIB_PAD_FROM_TO (0x51dc, 0x51e0); u32 vf_rx_enable[2]; u32 rx_timestamp_lo; CLIB_PAD_FROM_TO (0x51ec, 0x5200); /* 12 bits determined by multicast_control lookup bits in this vector. */ u32 multicast_enable[128]; /* [0] ethernet address [31:0] [1] [15:0] ethernet address [47:32] [31] valid bit. Index 0 is read from eeprom after reset. */ u32 rx_ethernet_address0[16][2]; CLIB_PAD_FROM_TO (0x5480, 0x5800); u32 wake_up_control; CLIB_PAD_FROM_TO (0x5804, 0x5808); u32 wake_up_filter_control; CLIB_PAD_FROM_TO (0x580c, 0x5818); u32 multiple_rx_queue_command_82598; CLIB_PAD_FROM_TO (0x581c, 0x5820); u32 management_control; u32 management_filter_control; CLIB_PAD_FROM_TO (0x5828, 0x5838); u32 wake_up_ip4_address_valid; CLIB_PAD_FROM_TO (0x583c, 0x5840); u32 wake_up_ip4_address_table[4]; u32 management_control_to_host; CLIB_PAD_FROM_TO (0x5854, 0x5880); u32 wake_up_ip6_address_table[4]; /* unicast_and broadcast_and vlan_and ip_address_and etc. */ u32 management_decision_filters[8]; u32 management_ip4_or_ip6_address_filters[4][4]; CLIB_PAD_FROM_TO (0x58f0, 0x5900); u32 wake_up_packet_length; CLIB_PAD_FROM_TO (0x5904, 0x5910); u32 management_ethernet_address_filters[4][2]; CLIB_PAD_FROM_TO (0x5930, 0x5a00); u32 wake_up_packet_memory[32]; CLIB_PAD_FROM_TO (0x5a80, 0x5c00); u32 redirection_table_82598[32]; u32 rss_random_keys_82598[10]; CLIB_PAD_FROM_TO (0x5ca8, 0x6000); ixge_dma_regs_t tx_dma[128]; u32 pf_vm_vlan_insert[64]; u32 tx_dma_tcp_max_alloc_size_requests; CLIB_PAD_FROM_TO (0x8104, 0x8110); u32 vf_tx_enable[2]; CLIB_PAD_FROM_TO (0x8118, 0x8120); /* [0] dcb mode enable [1] virtualization mode enable [3:2] number of tcs/qs per pool. */ u32 multiple_tx_queues_command; CLIB_PAD_FROM_TO (0x8124, 0x8200); u32 pf_vf_anti_spoof[8]; u32 pf_dma_tx_switch_control; CLIB_PAD_FROM_TO (0x8224, 0x82e0); u32 tx_strict_low_latency_queues[4]; CLIB_PAD_FROM_TO (0x82f0, 0x8600); u32 tx_queue_stats_mapping_82599[32]; u32 tx_queue_packet_counts[32]; u32 tx_queue_byte_counts[32][2]; struct { u32 control; u32 status; u32 buffer_almost_full; CLIB_PAD_FROM_TO (0x880c, 0x8810); u32 buffer_min_ifg; CLIB_PAD_FROM_TO (0x8814, 0x8900); } tx_security; struct { u32 index; u32 salt; u32 key[4]; CLIB_PAD_FROM_TO (0x8918, 0x8a00); } tx_ipsec; struct { u32 capabilities; u32 control; u32 tx_sci[2]; u32 sa; u32 sa_pn[2]; u32 key[2][4]; /* untagged packets, encrypted packets, protected packets, encrypted bytes, protected bytes */ u32 stats[5]; CLIB_PAD_FROM_TO (0x8a50, 0x8c00); } tx_link_security; struct { u32 control; u32 timestamp_value[2]; u32 system_time[2]; u32 increment_attributes; u32 time_adjustment_offset[2]; u32 aux_control; u32 target_time[2][2]; CLIB_PAD_FROM_TO (0x8c34, 0x8c3c); u32 aux_time_stamp[2][2]; CLIB_PAD_FROM_TO (0x8c4c, 0x8d00); } tx_timesync; struct { u32 control; u32 status; CLIB_PAD_FROM_TO (0x8d08, 0x8e00); } rx_security; struct { u32 index; u32 ip_address[4]; u32 spi; u32 ip_index; u32 key[4]; u32 salt; u32 mode; CLIB_PAD_FROM_TO (0x8e34, 0x8f00); } rx_ipsec; struct { u32 capabilities; u32 control; u32 sci[2]; u32 sa[2]; u32 sa_pn[2]; u32 key[2][4]; /* see datasheet */ u32 stats[17]; CLIB_PAD_FROM_TO (0x8f84, 0x9000); } rx_link_security; /* 4 wake up, 2 management, 2 wake up. */ u32 flexible_filters[8][16][4]; CLIB_PAD_FROM_TO (0x9800, 0xa000); /* 4096 bits. */ u32 vlan_filter[128]; /* [0] ethernet address [31:0] [1] [15:0] ethernet address [47:32] [31] valid bit. Index 0 is read from eeprom after reset. */ u32 rx_ethernet_address1[128][2]; /* select one of 64 pools for each rx address. */ u32 rx_ethernet_address_pool_select[128][2]; CLIB_PAD_FROM_TO (0xaa00, 0xc800); u32 tx_priority_to_traffic_class; CLIB_PAD_FROM_TO (0xc804, 0xcc00); /* In bytes units of 1k. Total packet buffer is 160k. */ u32 tx_packet_buffer_size[8]; CLIB_PAD_FROM_TO (0xcc20, 0xcd10); u32 tx_manageability_tc_mapping; CLIB_PAD_FROM_TO (0xcd14, 0xcd20); u32 dcb_tx_packet_plane_t2_config[8]; u32 dcb_tx_packet_plane_t2_status[8]; CLIB_PAD_FROM_TO (0xcd60, 0xce00); u32 tx_flow_control_status; CLIB_PAD_FROM_TO (0xce04, 0xd000); ixge_dma_regs_t rx_dma1[64]; struct { /* Bigendian ip4 src/dst address. */ u32 src_address[128]; u32 dst_address[128]; /* TCP/UDP ports [15:0] src [31:16] dst; bigendian. */ u32 tcp_udp_port[128]; /* [1:0] protocol tcp, udp, sctp, other [4:2] match priority (highest wins) [13:8] pool [25] src address match disable [26] dst address match disable [27] src port match disable [28] dst port match disable [29] protocol match disable [30] pool match disable [31] enable. */ u32 control[128]; /* [12] size bypass [19:13] must be 0x80 [20] low-latency interrupt [27:21] rx queue. */ u32 interrupt[128]; } ip4_filters; CLIB_PAD_FROM_TO (0xea00, 0xeb00); /* 4 bit rss output index indexed by 7 bit hash. 128 8 bit fields = 32 registers. */ u32 redirection_table_82599[32]; u32 rss_random_key_82599[10]; CLIB_PAD_FROM_TO (0xeba8, 0xec00); /* [15:0] reserved [22:16] rx queue index [29] low-latency interrupt on match [31] enable */ u32 ethernet_type_queue_select[8]; CLIB_PAD_FROM_TO (0xec20, 0xec30); u32 syn_packet_queue_filter; CLIB_PAD_FROM_TO (0xec34, 0xec60); u32 immediate_interrupt_rx_vlan_priority; CLIB_PAD_FROM_TO (0xec64, 0xec70); u32 rss_queues_per_traffic_class; CLIB_PAD_FROM_TO (0xec74, 0xec90); u32 lli_size_threshold; CLIB_PAD_FROM_TO (0xec94, 0xed00); struct { u32 control; CLIB_PAD_FROM_TO (0xed04, 0xed10); u32 table[8]; CLIB_PAD_FROM_TO (0xed30, 0xee00); } fcoe_redirection; struct { /* [1:0] packet buffer allocation 0 => disabled, else 64k*2^(f-1) [3] packet buffer initialization done [4] perfetch match mode [5] report status in rss field of rx descriptors [7] report status always [14:8] drop queue [20:16] flex 2 byte packet offset (units of 2 bytes) [27:24] max linked list length [31:28] full threshold. */ u32 control; CLIB_PAD_FROM_TO (0xee04, 0xee0c); u32 data[8]; /* [1:0] 0 => no action, 1 => add, 2 => remove, 3 => query. [2] valid filter found by query command [3] filter update override [4] ip6 adress table [6:5] l4 protocol reserved, udp, tcp, sctp [7] is ip6 [8] clear head/tail [9] packet drop action [10] matched packet generates low-latency interrupt [11] last in linked list [12] collision [15] rx queue enable [22:16] rx queue [29:24] pool. */ u32 command; CLIB_PAD_FROM_TO (0xee30, 0xee3c); /* ip4 dst/src address, tcp ports, udp ports. set bits mean bit is ignored. */ u32 ip4_masks[4]; u32 filter_length; u32 usage_stats; u32 failed_usage_stats; u32 filters_match_stats; u32 filters_miss_stats; CLIB_PAD_FROM_TO (0xee60, 0xee68); /* Lookup, signature. */ u32 hash_keys[2]; /* [15:0] ip6 src address 1 bit per byte [31:16] ip6 dst address. */ u32 ip6_mask; /* [0] vlan id [1] vlan priority [2] pool [3] ip protocol [4] flex [5] dst ip6. */ u32 other_mask; CLIB_PAD_FROM_TO (0xee78, 0xf000); } flow_director; struct { u32 l2_control[64]; u32 vlan_pool_filter[64]; u32 vlan_pool_filter_bitmap[128]; u32 dst_ethernet_address[128]; u32 mirror_rule[4]; u32 mirror_rule_vlan[8]; u32 mirror_rule_pool[8]; CLIB_PAD_FROM_TO (0xf650, 0x10010); } pf_bar; u32 eeprom_flash_control; /* [0] start [1] done [15:2] address [31:16] read data. */ u32 eeprom_read; CLIB_PAD_FROM_TO (0x10018, 0x1001c); u32 flash_access; CLIB_PAD_FROM_TO (0x10020, 0x10114); u32 flash_data; u32 flash_control; u32 flash_read_data; CLIB_PAD_FROM_TO (0x10120, 0x1013c); u32 flash_opcode; u32 software_semaphore; CLIB_PAD_FROM_TO (0x10144, 0x10148); u32 firmware_semaphore; CLIB_PAD_FROM_TO (0x1014c, 0x10160); u32 software_firmware_sync; CLIB_PAD_FROM_TO (0x10164, 0x10200); u32 general_rx_control; CLIB_PAD_FROM_TO (0x10204, 0x11000); struct { u32 control; CLIB_PAD_FROM_TO (0x11004, 0x11010); /* [3:0] enable counters [7:4] leaky bucket counter mode [29] reset [30] stop [31] start. */ u32 counter_control; /* [7:0],[15:8],[23:16],[31:24] event for counters 0-3. event codes: 0x0 bad tlp 0x10 reqs that reached timeout etc. */ u32 counter_event; CLIB_PAD_FROM_TO (0x11018, 0x11020); u32 counters_clear_on_read[4]; u32 counter_config[4]; struct { u32 address; u32 data; } indirect_access; CLIB_PAD_FROM_TO (0x11048, 0x11050); u32 extended_control; CLIB_PAD_FROM_TO (0x11054, 0x11064); u32 mirrored_revision_id; CLIB_PAD_FROM_TO (0x11068, 0x11070); u32 dca_requester_id_information; /* [0] global disable [4:1] mode: 0 => legacy, 1 => dca 1.0. */ u32 dca_control; CLIB_PAD_FROM_TO (0x11078, 0x110b0); /* [0] pci completion abort [1] unsupported i/o address [2] wrong byte enable [3] pci timeout */ u32 pcie_interrupt_status; CLIB_PAD_FROM_TO (0x110b4, 0x110b8); u32 pcie_interrupt_enable; CLIB_PAD_FROM_TO (0x110bc, 0x110c0); u32 msi_x_pba_clear[8]; CLIB_PAD_FROM_TO (0x110e0, 0x12300); } pcie; u32 interrupt_throttle1[128 - 24]; CLIB_PAD_FROM_TO (0x124a0, 0x14f00); u32 core_analog_config; CLIB_PAD_FROM_TO (0x14f04, 0x14f10); u32 core_common_config; CLIB_PAD_FROM_TO (0x14f14, 0x15f14); u32 link_sec_software_firmware_interface; } ixge_regs_t; typedef union { struct { /* Addresses bigendian. */ union { struct { ip6_address_t src_address; u32 unused[1]; } ip6; struct { u32 unused[3]; ip4_address_t src_address, dst_address; } ip4; }; /* [15:0] src port (little endian). [31:16] dst port. */ u32 tcp_udp_ports; /* [15:0] vlan (cfi bit set to 0). [31:16] flex bytes. bigendian. */ u32 vlan_and_flex_word; /* [14:0] hash [15] bucket valid [31:16] signature (signature filers)/sw-index (perfect match). */ u32 hash; }; u32 as_u32[8]; } ixge_flow_director_key_t; always_inline void ixge_throttle_queue_interrupt (ixge_regs_t * r, u32 queue_interrupt_index, f64 inter_interrupt_interval_in_secs) { volatile u32 *tr = (queue_interrupt_index < ARRAY_LEN (r->interrupt.throttle0) ? &r->interrupt.throttle0[queue_interrupt_index] : &r->interrupt_throttle1[queue_interrupt_index]); ASSERT (queue_interrupt_index < 128); u32 v; i32 i, mask = (1 << 9) - 1; i = flt_round_nearest (inter_interrupt_interval_in_secs / 2e-6); i = i < 1 ? 1 : i; i = i >= mask ? mask : i; v = tr[0]; v &= ~(mask << 3); v |= i << 3; tr[0] = v; } #define foreach_ixge_counter \ _ (0x40d0, rx_total_packets) \ _64 (0x40c0, rx_total_bytes) \ _ (0x41b0, rx_good_packets_before_filtering) \ _64 (0x41b4, rx_good_bytes_before_filtering) \ _ (0x2f50, rx_dma_good_packets) \ _64 (0x2f54, rx_dma_good_bytes) \ _ (0x2f5c, rx_dma_duplicated_good_packets) \ _64 (0x2f60, rx_dma_duplicated_good_bytes) \ _ (0x2f68, rx_dma_good_loopback_packets) \ _64 (0x2f6c, rx_dma_good_loopback_bytes) \ _ (0x2f74, rx_dma_good_duplicated_loopback_packets) \ _64 (0x2f78, rx_dma_good_duplicated_loopback_bytes) \ _ (0x4074, rx_good_packets) \ _64 (0x4088, rx_good_bytes) \ _ (0x407c, rx_multicast_packets) \ _ (0x4078, rx_broadcast_packets) \ _ (0x405c, rx_64_byte_packets) \ _ (0x4060, rx_65_127_byte_packets) \ _ (0x4064, rx_128_255_byte_packets) \ _ (0x4068, rx_256_511_byte_packets) \ _ (0x406c, rx_512_1023_byte_packets) \ _ (0x4070, rx_gt_1023_byte_packets) \ _ (0x4000, rx_crc_errors) \ _ (0x4120, rx_ip_checksum_errors) \ _ (0x4004, rx_illegal_symbol_errors) \ _ (0x4008, rx_error_symbol_errors) \ _ (0x4034, rx_mac_local_faults) \ _ (0x4038, rx_mac_remote_faults) \ _ (0x4040, rx_length_errors) \ _ (0x41a4, rx_xons) \ _ (0x41a8, rx_xoffs) \ _ (0x40a4, rx_undersize_packets) \ _ (0x40a8, rx_fragments) \ _ (0x40ac, rx_oversize_packets) \ _ (0x40b0, rx_jabbers) \ _ (0x40b4, rx_management_packets) \ _ (0x40b8, rx_management_drops) \ _ (0x3fa0, rx_missed_packets_pool_0) \ _ (0x40d4, tx_total_packets) \ _ (0x4080, tx_good_packets) \ _64 (0x4090, tx_good_bytes) \ _ (0x40f0, tx_multicast_packets) \ _ (0x40f4, tx_broadcast_packets) \ _ (0x87a0, tx_dma_good_packets) \ _64 (0x87a4, tx_dma_good_bytes) \ _ (0x40d8, tx_64_byte_packets) \ _ (0x40dc, tx_65_127_byte_packets) \ _ (0x40e0, tx_128_255_byte_packets) \ _ (0x40e4, tx_256_511_byte_packets) \ _ (0x40e8, tx_512_1023_byte_packets) \ _ (0x40ec, tx_gt_1023_byte_packets) \ _ (0x4010, tx_undersize_drops) \ _ (0x8780, switch_security_violation_packets) \ _ (0x5118, fc_crc_errors) \ _ (0x241c, fc_rx_drops) \ _ (0x2424, fc_last_error_count) \ _ (0x2428, fcoe_rx_packets) \ _ (0x242c, fcoe_rx_dwords) \ _ (0x8784, fcoe_tx_packets) \ _ (0x8788, fcoe_tx_dwords) \ _ (0x1030, queue_0_rx_count) \ _ (0x1430, queue_0_drop_count) \ _ (0x1070, queue_1_rx_count) \ _ (0x1470, queue_1_drop_count) \ _ (0x10b0, queue_2_rx_count) \ _ (0x14b0, queue_2_drop_count) \ _ (0x10f0, queue_3_rx_count) \ _ (0x14f0, queue_3_drop_count) \ _ (0x1130, queue_4_rx_count) \ _ (0x1530, queue_4_drop_count) \ _ (0x1170, queue_5_rx_count) \ _ (0x1570, queue_5_drop_count) \ _ (0x11b0, queue_6_rx_count) \ _ (0x15b0, queue_6_drop_count) \ _ (0x11f0, queue_7_rx_count) \ _ (0x15f0, queue_7_drop_count) \ _ (0x1230, queue_8_rx_count) \ _ (0x1630, queue_8_drop_count) \ _ (0x1270, queue_9_rx_count) \ _ (0x1270, queue_9_drop_count) typedef enum { #define _(a,f) IXGE_COUNTER_##f, #define _64(a,f) _(a,f) foreach_ixge_counter #undef _ #undef _64 IXGE_N_COUNTER, } ixge_counter_type_t; typedef struct { u32 mdio_address; /* 32 bit ID read from ID registers. */ u32 id; } ixge_phy_t; typedef struct { /* Cache aligned descriptors. */ ixge_descriptor_t *descriptors; /* Number of descriptors in table. */ u32 n_descriptors; /* Software head and tail pointers into descriptor ring. */ u32 head_index, tail_index; /* Index into dma_queues vector. */ u32 queue_index; /* Buffer indices corresponding to each active descriptor. */ u32 *descriptor_buffer_indices; union { struct { u32 *volatile head_index_write_back; u32 n_buffers_on_ring; } tx; struct { /* Buffer indices to use to replenish each descriptor. */ u32 *replenish_buffer_indices; vlib_node_runtime_t *node; u32 next_index; u32 saved_start_of_packet_buffer_index; u32 saved_start_of_packet_next_index; u32 saved_last_buffer_index; u32 is_start_of_packet; u32 n_descriptors_done_total; u32 n_descriptors_done_this_call; u32 n_bytes; } rx; }; } ixge_dma_queue_t; #define foreach_ixge_pci_device_id \ _ (82598, 0x10b6) \ _ (82598_bx, 0x1508) \ _ (82598af_dual_port, 0x10c6) \ _ (82598af_single_port, 0x10c7) \ _ (82598at, 0x10c8) \ _ (82598at2, 0x150b) \ _ (82598eb_sfp_lom, 0x10db) \ _ (82598eb_cx4, 0x10dd) \ _ (82598_cx4_dual_port, 0x10ec) \ _ (82598_da_dual_port, 0x10f1) \ _ (82598_sr_dual_port_em, 0x10e1) \ _ (82598eb_xf_lr, 0x10f4) \ _ (82599_kx4, 0x10f7) \ _ (82599_kx4_mezz, 0x1514) \ _ (82599_kr, 0x1517) \ _ (82599_combo_backplane, 0x10f8) \ _ (82599_cx4, 0x10f9) \ _ (82599_sfp, 0x10fb) \ _ (82599_backplane_fcoe, 0x152a) \ _ (82599_sfp_fcoe, 0x1529) \ _ (82599_sfp_em, 0x1507) \ _ (82599_xaui_lom, 0x10fc) \ _ (82599_t3_lom, 0x151c) \ _ (x540t, 0x1528) typedef enum { #define _(f,n) IXGE_##f = n, foreach_ixge_pci_device_id #undef _ } ixge_pci_device_id_t; typedef struct { /* registers */ ixge_regs_t *regs; /* Specific next index when using dynamic redirection */ u32 per_interface_next_index; /* PCI bus info. */ vlib_pci_dev_handle_t pci_dev_handle; /* From PCI config space header. */ ixge_pci_device_id_t device_id; u16 device_index; /* 0 or 1. */ u16 pci_function; /* VLIB interface for this instance. */ u32 vlib_hw_if_index, vlib_sw_if_index; ixge_dma_queue_t *dma_queues[VLIB_N_RX_TX]; /* Phy index (0 or 1) and address on MDI bus. */ u32 phy_index; ixge_phy_t phys[2]; /* Value of link_status register at last link change. */ u32 link_status_at_last_link_change; i2c_bus_t i2c_bus; sfp_eeprom_t sfp_eeprom; /* Counters. */ u64 counters[IXGE_N_COUNTER], counters_last_clear[IXGE_N_COUNTER]; } ixge_device_t; typedef struct { vlib_main_t *vlib_main; /* Vector of devices. */ ixge_device_t *devices; /* Descriptor ring sizes. */ u32 n_descriptors[VLIB_N_RX_TX]; /* RX buffer size. Must be at least 1k; will be rounded to next largest 1k size. */ u32 n_bytes_in_rx_buffer; u32 n_descriptors_per_cache_line; u32 process_node_index; /* Template and mask for initializing/validating TX descriptors. */ ixge_tx_descriptor_t tx_descriptor_template, tx_descriptor_template_mask; /* Vector of buffers for which TX is done and can be freed. */ u32 *tx_buffers_pending_free; u32 *rx_buffers_to_add; f64 time_last_stats_update; vlib_physmem_region_index_t physmem_region; int physmem_region_allocated; } ixge_main_t; extern ixge_main_t ixge_main; extern vnet_device_class_t ixge_device_class; typedef enum { IXGE_RX_NEXT_IP4_INPUT, IXGE_RX_NEXT_IP6_INPUT, IXGE_RX_NEXT_ETHERNET_INPUT, IXGE_RX_NEXT_DROP, IXGE_RX_N_NEXT, } ixge_rx_next_t; void ixge_set_next_node (ixge_rx_next_t, char *); #endif /* included_ixge_h */ /* * fd.io coding-style-patch-verification: ON * * Local Variables: * eval: (c-set-style "gnu") * End: */