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/*
 * Copyright (c) 2015 Cisco and/or its affiliates.
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at:
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/*
 * pipeline.h: software pipeline infrastructure
 *
 * Copyright (c) 2010 Eliot Dresselhaus
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice shall be
 * included in all copies or substantial portions of the Software.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *  NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
 *  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 *  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 *  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef included_clib_pipeline_h
#define included_clib_pipeline_h

#define clib_pipeline_stage(F,TYPE,ARG,I,BODY)		\
  always_inline void F##_inline (void * _, u32 I)	\
  { TYPE ARG = _; { BODY; } }				\
  never_inline  void F##_no_inline (TYPE ARG, u32 I)	\
  { F##_inline (ARG, I); }

#define clib_pipeline_stage_static(F,TYPE,ARG,I,BODY)		\
  static_always_inline void F##_inline (void * _, u32 I)	\
  { TYPE ARG = _; { BODY; } }					\
  never_inline  void F##_no_inline (TYPE ARG, u32 I)		\
  { F##_inline (ARG, I); }

#define clib_pipeline_stage_no_inline(F,TYPE,ARG,I,BODY)	\
  never_inline void F##_no_inline (void * _, u32 I)		\
  { TYPE ARG = _; { BODY; } }					\
  never_inline  void F##_inline (TYPE ARG, u32 I)		\
  { F##_no_inline (ARG, I); }

#define _clib_pipeline_var(v) _clib_pipeline_##v

#define clib_pipeline_stage_execute(F,A,I,S) \
  F##_##S (A, _clib_pipeline_var(i) - (I))

#define clib_pipeline_main_stage(F,A,I) \
  clib_pipeline_stage_execute (F, A, I, inline)
#define clib_pipeline_init_stage(F,A,I) \
  if (_clib_pipeline_var(i) >= (I)) clib_pipeline_stage_execute (F, A, I, no_inline)
#define clib_pipeline_exit_stage(F,A,I)					\
  if (_clib_pipeline_var(i) >= (I) && _clib_pipeline_var(i) - (I) < _clib_pipeline_var(n_vectors)) \
    clib_pipeline_stage_execute (F, A, I, no_inline)

#define clib_pipeline_init_loop				\
  for (_clib_pipeline_var(i) = 0;			\
       _clib_pipeline_var(i) <				\
	 clib_min (_clib_pipeline_var(n_stages) - 1,	\
		   _clib_pipeline_var(n_vectors));	\
       _clib_pipeline_var(i)++)

#define clib_pipeline_main_loop					\
  for (; _clib_pipeline_var(i) < _clib_pipeline_var(n_vectors);	\
       _clib_pipeline_var(i)++)

#define clib_pipeline_exit_loop						\
  for (; _clib_pipeline_var(i) < (_clib_pipeline_var(n_vectors)		\
				  + _clib_pipeline_var(n_stages) - 1);	\
       _clib_pipeline_var(i)++)

#define clib_pipeline_run_2_stage(N,ARG,STAGE0,STAGE1)	\
do {							\
  uword _clib_pipeline_var(n_vectors) = (N);		\
  uword _clib_pipeline_var(n_stages) = 2;		\
  uword _clib_pipeline_var(i);				\
							\
  clib_pipeline_init_loop				\
    {							\
      clib_pipeline_init_stage (STAGE0, ARG, 0);	\
    }							\
							\
  clib_pipeline_main_loop				\
    {							\
      clib_pipeline_main_stage (STAGE0, ARG, 0);	\
      clib_pipeline_main_stage (STAGE1, ARG, 1);	\
    }							\
							\
  clib_pipeline_exit_loop				\
    {							\
      clib_pipeline_exit_stage (STAGE1, ARG, 1);	\
    }							\
} while (0)

#define clib_pipeline_run_3_stage(N,ARG,STAGE0,STAGE1,STAGE2)	\
do {								\
  uword _clib_pipeline_var(n_vectors) = (N);			\
  uword _clib_pipeline_var(n_stages) = 3;			\
  uword _clib_pipeline_var(i);					\
								\
  clib_pipeline_init_loop					\
    {								\
      clib_pipeline_init_stage (STAGE0, ARG, 0);		\
      clib_pipeline_init_stage (STAGE1, ARG, 1);		\
    }								\
								\
  clib_pipeline_main_loop					\
    {								\
      clib_pipeline_main_stage (STAGE0, ARG, 0);		\
      clib_pipeline_main_stage (STAGE1, ARG, 1);		\
      clib_pipeline_main_stage (STAGE2, ARG, 2);		\
    }								\
								\
  clib_pipeline_exit_loop					\
    {								\
      clib_pipeline_exit_stage (STAGE1, ARG, 1);		\
      clib_pipeline_exit_stage (STAGE2, ARG, 2);		\
    }								\
} while (0)

#define clib_pipeline_run_4_stage(N,ARG,STAGE0,STAGE1,STAGE2,STAGE3)	\
do {									\
  uword _clib_pipeline_var(n_vectors) = (N);				\
  uword _clib_pipeline_var(n_stages) = 4;				\
  uword _clib_pipeline_var(i);						\
									\
  clib_pipeline_init_loop						\
    {									\
      clib_pipeline_init_stage (STAGE0, ARG, 0);			\
      clib_pipeline_init_stage (STAGE1, ARG, 1);			\
      clib_pipeline_init_stage (STAGE2, ARG, 2);			\
    }									\
									\
  clib_pipeline_main_loop						\
    {									\
      clib_pipeline_main_stage (STAGE0, ARG, 0);			\
      clib_pipeline_main_stage (STAGE1, ARG, 1);			\
      clib_pipeline_main_stage (STAGE2, ARG, 2);			\
      clib_pipeline_main_stage (STAGE3, ARG, 3);			\
    }									\
									\
  clib_pipeline_exit_loop						\
    {									\
      clib_pipeline_exit_stage (STAGE1, ARG, 1);			\
      clib_pipeline_exit_stage (STAGE2, ARG, 2);			\
      clib_pipeline_exit_stage (STAGE3, ARG, 3);			\
    }									\
} while (0)

#endif /* included_clib_pipeline_h */

/*
 * fd.io coding-style-patch-verification: ON
 *
 * Local Variables:
 * eval: (c-set-style "gnu")
 * End:
 */
o/fdio/{release}`. For example see artifacts for the [VPP release 20.01](https://packagecloud.io/fdio/2101). The last available build is to be used. 1. All CSIT patches for the release are merged in CSIT master branch. ### Procedure **A. Release branch** 1. Open [Gerrit](https://gerrit.fd.io). 1. Go to [Browse --> Repositories --> csit --> Branches](https://gerrit.fd.io/r/admin/repos/csit,branches). 1. Save the revision string of master for further use. 1. Click `CREATE NEW`. 1. Fill in the revision number and the name of the new release branch. Its format is: `rlsYYMM`, e.g. rls2101. 1. Click "CREATE". **B. Jenkins jobs** See ["Add CSIT rls2101 branch"](https://gerrit.fd.io/r/c/ci-management/+/30439) and ["Add report jobs to csit rls2101 branch"](https://gerrit.fd.io/r/c/ci-management/+/30462) patches as an example. 1. [csit.yaml](https://github.com/FDio/ci-management/blob/master/jjb/csit/csit.yaml): Documentation of the source code and the Report - Add release branch (rls2101) for `csit-docs-merge-{stream}` and `csit-report-merge-{stream}` (project --> stream). 1. [csit-perf.yaml](https://github.com/FDio/ci-management/blob/master/jjb/csit/csit-perf.yaml): Verify jobs - Add release branch (rls2101) to `project --> jobs --> csit-vpp-perf-verify-{stream}-{node-arch} --> stream`. - Add release branch (rls2101) to `project --> project: 'csit' --> stream`. - Add release branch (rls2101) to `project --> project: 'csit' --> stream_report`. 1. [csit-tox.yaml](https://github.com/FDio/ci-management/blob/master/jjb/csit/csit-tox.yaml): tox - Add release branch (rls2101) to `project --> stream`. 1. [csit-vpp-device.yaml](https://github.com/FDio/ci-management/blob/master/jjb/csit/csit-vpp-device.yaml): csit-vpp-device - Add release branch (rls2101) to `project --> jobs (weekly / semiweekly) --> stream`. - Add release branch (rls2101) to `project --> project: 'csit' --> stream`. **C. VPP Stable version** See the patch [Update of VPP_REPO_URL and VPP_STABLE_VER files](https://gerrit.fd.io/r/c/csit/+/30461) and / or [rls2101: Update VPP_STABLE_VER files to release version](https://gerrit.fd.io/r/c/csit/+/30976) as an example. 1. Find the last successful build on the [Package Cloud](https://packagecloud.io) for the release, e.g. [VPP release 20.01](https://packagecloud.io/fdio/2101). 1. Clone the release branch to your PC: `git clone --depth 1 ssh://<user>@gerrit.fd.io:29418/csit --branch rls{RELEASE}` 1. Modify [VPP_STABLE_VER_UBUNTU_BIONIC](../../VPP_STABLE_VER_UBUNTU_BIONIC) and [VPP_STABLE_VER_CENTOS](../../VPP_STABLE_VER_CENTOS) files with the last successful build. 1. Modify [VPP_REPO_URL](../../VPP_REPO_URL) to point to the new release, e.g. `https://packagecloud.io/install/repositories/fdio/2101`. 1. You can also modify the [.gitreview](../../.gitreview) file and set the new default branch. 1. Wait until the verify jobs - [csit-vpp-device-2101-ubuntu1804-1n-skx](https://jenkins.fd.io/job/csit-vpp-device-2101-ubuntu1804-1n-skx) - [csit-vpp-device-2101-ubuntu1804-1n-tx2](https://jenkins.fd.io/job/csit-vpp-device-2101-ubuntu1804-1n-tx2) successfully finish and merge the patch. **D. CSIT Operational Branch** 1. Manually start (Build with Parameters) the weekly job [csit-vpp-device-2101-ubuntu1804-1n-skx-weekly](https://jenkins.fd.io/view/csit/job/csit-vpp-device-2101-ubuntu1804-1n-skx-weekly) 1. When it successfully finishes, take the revision string e.g. **Revision**: 876b6c1ae05bfb1ad54ff253ea021f3b46780fd4 to create a new operational branch for the new release. 1. Open [Gerrit](https://gerrit.fd.io). 1. Go to [Browse --> Repositories --> csit --> Branches](https://gerrit.fd.io/r/admin/repos/csit,branches). 1. Click `CREATE NEW`. 1. Fill in the revision number and the name of the new operational branch. Its format is: `oper-rls{RELEASE}-YYMMDD` e.g. `oper-rls2101-201217`. 1. Click "CREATE". 1. Manually start (Build with Parameters) the semiweekly job [csit-vpp-device-2101-ubuntu1804-1n-skx-semiweekly](https://jenkins.fd.io/view/csit/job/csit-vpp-device-2101-ubuntu1804-1n-skx-semiweekly) 1. When it successfully finishes check in console log if it used the right VPP version (search for `VPP_VERSION=`) from the right repository (search for `REPO_URL=`). **E. Announcement** If everything is as it should be, send the announcement email to `csit-dev@lists.fd.io` mailing list. *Example:* Subject: ```text CSIT rls2101 branch pulled out ``` Body: ```text CSIT rls2101 branch [0] is created and fully functional. Corresponding operational branch (oper-rls2101-201217) has been created too. We are starting dry runs for performance ndrpdr iterative tests to get initial ndrpdr values with available rc1 packages as well as to test all the infra before starting report data collection runs. Regards, <signature> [0] https://git.fd.io/csit/log/?h=rls2101 ```