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/*
 * Copyright (c) 2015 Cisco and/or its affiliates.
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at:
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef included_clib_timing_wheel_h
#define included_clib_timing_wheel_h

#include <vppinfra/format.h>

typedef struct
{
  /* Time of this element in units cpu clock ticks relative to time
     base. 32 bits should be large enough for several kilo-seconds
     to elapse before we have to re-set time base. */
  u32 cpu_time_relative_to_base;

  /* User data to store in this bin. */
  u32 user_data;
} timing_wheel_elt_t;

/* Overflow wheel elements where time does not fit into 32 bits. */
typedef struct
{
  /* Absolute time of this element. */
  u64 cpu_time;

  /* User data to store in this bin. */
  u32 user_data;

  u32 pad;
} timing_wheel_overflow_elt_t;

typedef struct
{
  /* 2^M bits: 1 means vector is non-zero else zero. */
  uword *occupancy_bitmap;

  /* 2^M element table of element vectors, one for each time bin. */
  timing_wheel_elt_t **elts;
} timing_wheel_level_t;

typedef struct
{
  /* Vector of refill counts per level. */
  u64 *refills;

  /* Number of times cpu time base was rescaled. */
  u64 cpu_time_base_advances;
} timing_wheel_stats_t;

typedef struct
{
  /* Each bin is a power of two clock ticks (N)
     chosen so that 2^N >= min_sched_time. */
  u8 log2_clocks_per_bin;

  /* Wheels are 2^M bins where 2^(N+M) >= max_sched_time. */
  u8 log2_bins_per_wheel;

  /* N + M. */
  u8 log2_clocks_per_wheel;

  /* Number of bits to use in cpu_time_relative_to_base field
     of timing_wheel_elt_t. */
  u8 n_wheel_elt_time_bits;

  /* 2^M. */
  u32 bins_per_wheel;

  /* 2^M - 1. */
  u32 bins_per_wheel_mask;

  timing_wheel_level_t *levels;

  timing_wheel_overflow_elt_t *overflow_pool;

  /* Free list of element vector so we can recycle old allocated vectors. */
  timing_wheel_elt_t **free_elt_vectors;

  timing_wheel_elt_t *unexpired_elts_pending_insert;

  /* Hash table of user data values which have been deleted but not yet re-inserted. */
  uword *deleted_user_data_hash;

  /* Enable validation for debugging. */
  u32 validate;

  /* Time index.  Measures time in units of 2^N clock ticks from
     when wheel starts. */
  u64 current_time_index;

  /* All times are 32 bit numbers relative to cpu_time_base.
     So, roughly every 2^(32 + N) clocks we'll need to subtract from
     all timing_wheel_elt_t times to make sure they never overflow. */
  u64 cpu_time_base;

  /* When current_time_index is >= this we update cpu_time_base
     to avoid overflowing 32 bit cpu_time_relative_to_base
     in timing_wheel_elt_t. */
  u64 time_index_next_cpu_time_base_update;

  /* Cached earliest element on wheel; 0 if not valid. */
  u64 cached_min_cpu_time_on_wheel;

  f64 min_sched_time, max_sched_time, cpu_clocks_per_second;

  timing_wheel_stats_t stats;
} timing_wheel_t;

/* Initialization function. */
void timing_wheel_init (timing_wheel_t * w,
			u64 current_cpu_time, f64 cpu_clocks_per_second);

/* Insert user data on wheel at given CPU time stamp. */
void timing_wheel_insert (timing_wheel_t * w, u64 insert_cpu_time,
			  u32 user_data);

/* Delete user data from wheel (until it is again inserted). */
void timing_wheel_delete (timing_wheel_t * w, u32 user_data);

/* Advance wheel and return any expired user data in vector.  If non-zero
   min_next_expiring_element_cpu_time will return a cpu time stamp
   before which there are guaranteed to be no elements in the current wheel. */
u32 *timing_wheel_advance (timing_wheel_t * w, u64 advance_cpu_time,
			   u32 * expired_user_data,
			   u64 * min_next_expiring_element_cpu_time);

/* Returns absolute time in clock cycles of next expiring element. */
u64 timing_wheel_next_expiring_elt_time (timing_wheel_t * w);

/* Format a timing wheel. */
format_function_t format_timing_wheel;

/* Testing function to validate wheel. */
void timing_wheel_validate (timing_wheel_t * w);

#endif /* included_clib_timing_wheel_h */

/*
 * fd.io coding-style-patch-verification: ON
 *
 * Local Variables:
 * eval: (c-set-style "gnu")
 * End:
 */
plate | Local Template | | Documentation | *RFC2544: Packet throughput L2BD test cases with ACL* | | ... | *[Top] Network Topologies:* TG-DUT1-DUT2-TG 3-node circular topology\ | ... | with single links between nodes. | ... | *[Enc] Packet Encapsulations:* Eth-IPv4 for L2 switching of IPv4. | ... | *[Cfg] DUT configuration:* DUT1 is configured with L2 bridge domain\ | ... | and MAC learning enabled. DUT2 is configured with L2 cross-connects.\ | ... | Required MACIP ACL rules are applied to input paths of both DUT1\ | ... | interfaces. DUT1 and DUT2 are tested with ${nic_name}.\ | ... | *[Ver] TG verification:* TG finds and reports throughput NDR (Non Drop\ | ... | Rate) with zero packet loss tolerance and throughput PDR (Partial Drop\ | ... | Rate) with non-zero packet loss tolerance (LT) expressed in percentage\ | ... | of packets transmitted. NDR and PDR are discovered for different\ | ... | Ethernet L2 frame sizes using MLRsearch library.\ | ... | Test packets are generated by TG on\ | ... | links to DUTs. TG traffic profile contains two L3 flow-groups\ | ... | (flow-group per direction, ${flows_per_dir} flows per flow-group) with\ | ... | all packets containing Ethernet header, IPv4 header with IP protocol=61\ | ... | and static payload. MAC addresses are matching MAC addresses of the TG\ | ... | node interfaces. | ... | *[Ref] Applicable standard specifications:* RFC2544. *** Variables *** | @{plugins_to_enable}= | dpdk_plugin.so | acl_plugin.so | ${crypto_type}= | ${None} | ${nic_name}= | Intel-X710 | ${nic_driver}= | vfio-pci | ${nic_rxq_size}= | 0 | ${nic_txq_size}= | 0 | ${nic_pfs}= | 2 | ${nic_vfs}= | 0 | ${osi_layer}= | L2 | ${overhead}= | ${0} # ACL test setup | ${acl_action}= | permit | ${no_hit_aces_number}= | 50 | ${flows_per_dir}= | 100 # starting points for non-hitting ACLs | ${src_ip_start}= | 30.30.30.1 | ${ip_step}= | ${1} | ${src_mac_start}= | 01:02:03:04:05:06 | ${src_mac_step}= | ${1000} | ${src_mac_mask}= | 00:00:00:00:00:00 | ${tg_stream1_mac}= | ca:fe:00:00:00:00 | ${tg_stream2_mac}= | fa:ce:00:00:00:00 | ${tg_mac_mask}= | ff:ff:ff:ff:ff:80 | ${tg_stream1_subnet}= | 10.0.0.0/24 | ${tg_stream2_subnet}= | 20.0.0.0/24 # traffic profile | ${traffic_profile}= | trex-stl-3n-ethip4-macsrc100ip4src100 *** Keywords *** | Local Template | | [Documentation] | | ... | [Cfg] DUT runs IPv4 routing config. | | ... | Each DUT uses ${phy_cores} physical core(s) for worker threads. | | ... | [Ver] Measure NDR and PDR values using MLRsearch algorithm.\ | | | | ... | *Arguments:* | | ... | - frame_size - Framesize in Bytes in integer or string (IMIX_v4_1). | | ... | Type: integer, string | | ... | - phy_cores - Number of physical cores. Type: integer | | ... | - rxq - Number of RX queues, default value: ${None}. Type: integer | | | | [Arguments] | ${frame_size} | ${phy_cores} | ${rxq}=${None} | | | | Set Test Variable | \${frame_size} | | | | Given Set Max Rate And Jumbo | | And Add worker threads to all DUTs | ${phy_cores} | ${rxq} | | And Pre-initialize layer driver | ${nic_driver} | | And Apply Startup configuration on all VPP DUTs | | When Initialize layer driver | ${nic_driver} | | And Initialize layer interface | | And Initialize L2 bridge domain with MACIP ACLs in circular topology | | Then Find NDR and PDR intervals using optimized search *** Test Cases *** | 64B-1c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | 64B | 1C | | frame_size=${64} | phy_cores=${1} | 64B-2c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | 64B | 2C | | frame_size=${64} | phy_cores=${2} | 64B-4c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | 64B | 4C | | frame_size=${64} | phy_cores=${4} | 1518B-1c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | 1518B | 1C | | frame_size=${1518} | phy_cores=${1} | 1518B-2c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | 1518B | 2C | | frame_size=${1518} | phy_cores=${2} | 1518B-4c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | 1518B | 4C | | frame_size=${1518} | phy_cores=${4} | 9000B-1c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | 9000B | 1C | | frame_size=${9000} | phy_cores=${1} | 9000B-2c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | 9000B | 2C | | frame_size=${9000} | phy_cores=${2} | 9000B-4c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | 9000B | 4C | | frame_size=${9000} | phy_cores=${4} | IMIX-1c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | IMIX | 1C | | frame_size=IMIX_v4_1 | phy_cores=${1} | IMIX-2c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | IMIX | 2C | | frame_size=IMIX_v4_1 | phy_cores=${2} | IMIX-4c-eth-l2bdbasemaclrn-macip-iacl50sl-100flows-ndrpdr | | [Tags] | IMIX | 4C | | frame_size=IMIX_v4_1 | phy_cores=${4}