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path: root/test/test_ip4_irb.py
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#!/usr/bin/env python
"""IRB Test Case HLD:

**config**
    - L2 MAC learning enabled in l2bd
    - 2 routed interfaces untagged, bvi (Bridge Virtual Interface)
    - 2 bridged interfaces in l2bd with bvi

**test**
    - sending ip4 eth pkts between routed interfaces
        - 2 routed interfaces
        - 2 bridged interfaces

    - 64B, 512B, 1518B, 9200B (ether_size)

    - burst of pkts per interface
        - 257pkts per burst
        - routed pkts hitting different FIB entries
        - bridged pkts hitting different MAC entries

**verify**
    - all packets received correctly

"""

import unittest
from random import choice

from scapy.packet import Raw
from scapy.layers.l2 import Ether
from scapy.layers.inet import IP, UDP

from framework import VppTestCase, VppTestRunner
from vpp_papi import MACAddress
from vpp_l2 import L2_PORT_TYPE


class TestIpIrb(VppTestCase):
    """IRB Test Case"""

    @classmethod
    def setUpClass(cls):
        """
        #. Create BD with MAC learning enabled and put interfaces to this BD.
        #. Configure IPv4 addresses on BVI interface and routed interface.
        #. Configure MAC address binding to IPv4 neighbors on bvi0.
        #. Configure MAC address on pg2.
        #. BVI interface has remote hosts, one half of hosts are
           behind pg0 second behind pg1.
        """
        super(TestIpIrb, cls).setUpClass()

        cls.pg_if_packet_sizes = [64, 512, 1518, 9018]  # packet sizes
        cls.bd_id = 10
        cls.remote_hosts_count = 250

        # create 3 pg interfaces, 1 BVI interface
        cls.create_pg_interfaces(range(3))
        cls.create_bvi_interfaces(1)

        cls.interfaces = list(cls.pg_interfaces)
        cls.interfaces.extend(cls.bvi_interfaces)

        for i in cls.interfaces:
            i.admin_up()

        # Create BD with MAC learning enabled and put interfaces to this BD
        cls.vapi.sw_interface_set_l2_bridge(
            rx_sw_if_index=cls.bvi0.sw_if_index, bd_id=cls.bd_id,
            port_type=L2_PORT_TYPE.BVI)
        cls.vapi.sw_interface_set_l2_bridge(rx_sw_if_index=cls.pg0.sw_if_index,
                                            bd_id=cls.bd_id)
        cls.vapi.sw_interface_set_l2_bridge(rx_sw_if_index=cls.pg1.sw_if_index,
                                            bd_id=cls.bd_id)

        # Configure IPv4 addresses on BVI interface and routed interface
        cls.bvi0.config_ip4()
        cls.pg2.config_ip4()

        # Configure MAC address binding to IPv4 neighbors on bvi0
        cls.bvi0.generate_remote_hosts(cls.remote_hosts_count)
        cls.bvi0.configure_ipv4_neighbors()
        # configure MAC address on pg2
        cls.pg2.resolve_arp()

        # BVI interface has remote hosts, one half of hosts are behind
        # pg0 second behind pg1
        half = cls.remote_hosts_count // 2
        cls.pg0.remote_hosts = cls.bvi0.remote_hosts[:half]
        cls.pg1.remote_hosts = cls.bvi0.remote_hosts[half:]

    @classmethod
    def tearDownClass(cls):
        super(TestIpIrb, cls).tearDownClass()

    def tearDown(self):
        """Run standard test teardown and log ``show l2patch``,
        ``show l2fib verbose``,``show bridge-domain <bd_id> detail``,
        ``show ip arp``.
        """
        super(TestIpIrb, self).tearDown()

    def show_commands_at_teardown(self):
        self.logger.info(self.vapi.cli("show l2patch"))
        self.logger.info(self.vapi.cli("show l2fib verbose"))
        self.logger.info(self.vapi.cli("show bridge-domain %s detail" %
                                       self.bd_id))
        self.logger.info(self.vapi.cli("show ip arp"))

    def create_stream(self, src_ip_if, dst_ip_if, packet_sizes):
        pkts = []
        for i in range(0, 257):
            remote_dst_host = choice(dst_ip_if.remote_hosts)
            info = self.create_packet_info(src_ip_if, dst_ip_if)
            payload = self.info_to_payload(info)
            p = (Ether(dst=src_ip_if.local_mac, src=src_ip_if.remote_mac) /
                 IP(src=src_ip_if.remote_ip4,
                    dst=remote_dst_host.ip4) /
                 UDP(sport=1234, dport=1234) /
                 Raw(payload))
            info.data = p.copy()
            size = packet_sizes[(i // 2) % len(packet_sizes)]
            self.extend_packet(p, size)
            pkts.append(p)
        return pkts

    def create_stream_l2_to_ip(self, src_l2_if, src_ip_if, dst_ip_if,
                               packet_sizes):
        pkts = []
        for i in range(0, 257):
            info = self.create_packet_info(src_ip_if, dst_ip_if)
            payload = self.info_to_payload(info)

            host = choice(src_l2_if.remote_hosts)

            p = (Ether(src=host.mac,
                       dst=src_ip_if.local_mac) /
                 IP(src=host.ip4,
                    dst=dst_ip_if.remote_ip4) /
                 UDP(sport=1234, dport=1234) /
                 Raw(payload))

            info.data = p.copy()
            size = packet_sizes[(i // 2) % len(packet_sizes)]
            self.extend_packet(p, size)

            pkts.append(p)
        return pkts

    def verify_capture_l2_to_ip(self, dst_ip_if, src_ip_if, capture):
        last_info = dict()
        for i in self.interfaces:
            last_info[i.sw_if_index] = None

        dst_ip_sw_if_index = dst_ip_if.sw_if_index

        for packet in capture:
            ip = packet[IP]
            udp = packet[IP][UDP]
            payload_info = self.payload_to_info(packet[IP][UDP][Raw])

            self.assertEqual(payload_info.dst, dst_ip_sw_if_index)

            next_info = self.get_next_packet_info_for_interface2(
                payload_info.src, dst_ip_sw_if_index,
                last_info[payload_info.src])
            last_info[payload_info.src] = next_info
            self.assertTrue(next_info is not None)
            saved_packet = next_info.data
            self.assertTrue(next_info is not None)

            # MAC: src, dst
            self.assertEqual(packet.src, dst_ip_if.local_mac)
            self.assertEqual(packet.dst, dst_ip_if.remote_mac)

            # IP: src, dst
            host = src_ip_if.host_by_ip4(ip.src)
            self.assertIsNotNone(host)
            self.assertEqual(ip.dst, saved_packet[IP].dst)
            self.assertEqual(ip.dst, dst_ip_if.remote_ip4)

            # UDP:
            self.assertEqual(udp.sport, saved_packet[UDP].sport)
            self.assertEqual(udp.dport, saved_packet[UDP].dport)

    def verify_capture(self, dst_ip_if, src_ip_if, capture):
        last_info = dict()
        for i in self.interfaces:
            last_info[i.sw_if_index] = None

        dst_ip_sw_if_index = dst_ip_if.sw_if_index

        for packet in capture:
            ip = packet[IP]
            udp = packet[IP][UDP]
            payload_info = self.payload_to_info(packet[IP][UDP][Raw])
            packet_index = payload_info.index

            self.assertEqual(payload_info.dst, dst_ip_sw_if_index)

            next_info = self.get_next_packet_info_for_interface2(
                payload_info.src, dst_ip_sw_if_index,
                last_info[payload_info.src])
            last_info[payload_info.src] = next_info
            self.assertTrue(next_info is not None)
            self.assertEqual(packet_index, next_info.index)
            saved_packet = next_info.data
            self.assertTrue(next_info is not None)

            # MAC: src, dst
            self.assertEqual(packet.src, dst_ip_if.local_mac)
            host = dst_ip_if.host_by_mac(packet.dst)

            # IP: src, dst
            self.assertEqual(ip.src, src_ip_if.remote_ip4)
            self.assertEqual(ip.dst, saved_packet[IP].dst)
            self.assertEqual(ip.dst, host.ip4)

            # UDP:
            self.assertEqual(udp.sport, saved_packet[UDP].sport)
            self.assertEqual(udp.dport, saved_packet[UDP].dport)

    def test_ip4_irb_1(self):
        """ IPv4 IRB test 1

        Test scenario:
            - ip traffic from pg2 interface must ends in both pg0 and pg1
            - arp entry present in bvi0 interface for destination IP
            - no l2 entry configured, pg0 and pg1 are same
        """

        stream = self.create_stream(
            self.pg2, self.bvi0, self.pg_if_packet_sizes)
        self.pg2.add_stream(stream)

        self.pg_enable_capture(self.pg_interfaces)
        self.pg_start()

        packet_count = self.get_packet_count_for_if_idx(self.bvi0.sw_if_index)

        rcvd1 = self.pg0.get_capture(packet_count)
        rcvd2 = self.pg1.get_capture(packet_count)

        self.verify_capture(self.bvi0, self.pg2, rcvd1)
        self.verify_capture(self.bvi0, self.pg2, rcvd2)

        self.assertListEqual(rcvd1.res, rcvd2.res)

    def send_and_verify_l2_to_ip(self):
        stream1 = self.create_stream_l2_to_ip(
            self.pg0, self.bvi0, self.pg2, self.pg_if_packet_sizes)
        stream2 = self.create_stream_l2_to_ip(
            self.pg1, self.bvi0, self.pg2, self.pg_if_packet_sizes)
        self.vapi.cli("clear trace")
        self.pg0.add_stream(stream1)
        self.pg1.add_stream(stream2)

        self.pg_enable_capture(self.pg_interfaces)
        self.pg_start()

        rcvd = self.pg2.get_capture(514)
        self.verify_capture_l2_to_ip(self.pg2, self.bvi0, rcvd)

    def test_ip4_irb_2(self):
        """ IPv4 IRB test 2

        Test scenario:
            - ip traffic from pg0 and pg1 ends on pg2
        """
        self.send_and_verify_l2_to_ip()

        # change the BVI's mac and resed traffic
        self.bvi0.set_mac(MACAddress("00:00:00:11:11:33"))

        self.send_and_verify_l2_to_ip()
        # check it wasn't flooded
        self.pg1.assert_nothing_captured(remark="UU Flood")


if __name__ == '__main__':
    unittest.main(testRunner=VppTestRunner)
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#include <perfmon/perfmon_intel.h>

static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
  {0x4F, 0x00, 0},

};

static perfmon_intel_pmc_event_t event_table[] = {
  {
   .event_code = {0x00},
   .umask = 0x01,
   .event_name = "inst_retired.any",
   },
  {
   .event_code = {0x00},
   .umask = 0x02,
   .event_name = "cpu_clk_unhalted.thread",
   },
  {
   .event_code = {0x00},
   .umask = 0x02,
   .event_name = "cpu_clk_unhalted.thread_any",
   },
  {
   .event_code = {0x00},
   .umask = 0x03,
   .event_name = "cpu_clk_unhalted.ref_tsc",
   },
  {
   .event_code = {0x03},
   .umask = 0x02,
   .event_name = "ld_blocks.store_forward",
   },
  {
   .event_code = {0x03},
   .umask = 0x08,
   .event_name = "ld_blocks.no_sr",
   },
  {
   .event_code = {0x05},
   .umask = 0x01,
   .event_name = "misalign_mem_ref.loads",
   },
  {
   .event_code = {0x05},
   .umask = 0x02,
   .event_name = "misalign_mem_ref.stores",
   },
  {
   .event_code = {0x07},
   .umask = 0x01,
   .event_name = "ld_blocks_partial.address_alias",
   },
  {
   .event_code = {0x08},
   .umask = 0x01,
   .event_name = "dtlb_load_misses.miss_causes_a_walk",
   },
  {
   .event_code = {0x08},
   .umask = 0x02,
   .event_name = "dtlb_load_misses.walk_completed_4k",
   },
  {
   .event_code = {0x08},
   .umask = 0x04,
   .event_name = "dtlb_load_misses.walk_completed_2m_4m",
   },
  {
   .event_code = {0x08},
   .umask = 0x08,
   .event_name = "dtlb_load_misses.walk_completed_1g",
   },
  {
   .event_code = {0x08},
   .umask = 0x0e,
   .event_name = "dtlb_load_misses.walk_completed",
   },
  {
   .event_code = {0x08},
   .umask = 0x10,
   .event_name = "dtlb_load_misses.walk_duration",
   },
  {
   .event_code = {0x08},
   .umask = 0x20,
   .event_name = "dtlb_load_misses.stlb_hit_4k",
   },
  {
   .event_code = {0x08},
   .umask = 0x40,
   .event_name = "dtlb_load_misses.stlb_hit_2m",
   },
  {
   .event_code = {0x08},
   .umask = 0x60,
   .event_name = "dtlb_load_misses.stlb_hit",
   },
  {
   .event_code = {0x0D},
   .umask = 0x03,
   .event_name = "int_misc.recovery_cycles",
   },
  {
   .event_code = {0x0D},
   .umask = 0x03,
   .event_name = "int_misc.recovery_cycles_any",
   },
  {
   .event_code = {0x0D},
   .umask = 0x08,
   .event_name = "int_misc.rat_stall_cycles",
   },
  {
   .event_code = {0x0E},
   .umask = 0x01,
   .event_name = "uops_issued.any",
   },
  {
   .event_code = {0x0E},
   .umask = 0x01,
   .event_name = "uops_issued.stall_cycles",
   },
  {
   .event_code = {0x0E},
   .umask = 0x10,
   .event_name = "uops_issued.flags_merge",
   },
  {
   .event_code = {0x0E},
   .umask = 0x20,
   .event_name = "uops_issued.slow_lea",
   },
  {
   .event_code = {0x0E},
   .umask = 0x40,
   .event_name = "uops_issued.single_mul",
   },
  {
   .event_code = {0x14},
   .umask = 0x01,
   .event_name = "arith.fpu_div_active",
   },
  {
   .event_code = {0x24},
   .umask = 0x21,
   .event_name = "l2_rqsts.demand_data_rd_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x22,
   .event_name = "l2_rqsts.rfo_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x24,
   .event_name = "l2_rqsts.code_rd_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x27,
   .event_name = "l2_rqsts.all_demand_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x30,
   .event_name = "l2_rqsts.l2_pf_miss",
   },
  {
   .event_code = {0x24},
   .umask = 0x3F,
   .event_name = "l2_rqsts.miss",
   },
  {
   .event_code = {0x24},
   .umask = 0xc1,
   .event_name = "l2_rqsts.demand_data_rd_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0xc2,
   .event_name = "l2_rqsts.rfo_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0xc4,
   .event_name = "l2_rqsts.code_rd_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0xd0,
   .event_name = "l2_rqsts.l2_pf_hit",
   },
  {
   .event_code = {0x24},
   .umask = 0xE1,
   .event_name = "l2_rqsts.all_demand_data_rd",
   },
  {
   .event_code = {0x24},
   .umask = 0xE2,
   .event_name = "l2_rqsts.all_rfo",
   },
  {
   .event_code = {0x24},
   .umask = 0xE4,
   .event_name = "l2_rqsts.all_code_rd",
   },
  {
   .event_code = {0x24},
   .umask = 0xe7,
   .event_name = "l2_rqsts.all_demand_references",
   },
  {
   .event_code = {0x24},
   .umask = 0xF8,
   .event_name = "l2_rqsts.all_pf",
   },
  {
   .event_code = {0x24},
   .umask = 0xFF,
   .event_name = "l2_rqsts.references",
   },
  {
   .event_code = {0x27},
   .umask = 0x50,
   .event_name = "l2_demand_rqsts.wb_hit",
   },
  {
   .event_code = {0x2E},
   .umask = 0x41,
   .event_name = "longest_lat_cache.miss",
   },
  {
   .event_code = {0x2E},
   .umask = 0x4F,
   .event_name = "longest_lat_cache.reference",
   },
  {
   .event_code = {0x3C},
   .umask = 0x00,
   .event_name = "cpu_clk_unhalted.thread_p",
   },
  {
   .event_code = {0x3C},
   .umask = 0x00,
   .event_name = "cpu_clk_unhalted.thread_p_any",
   },
  {
   .event_code = {0x3C},
   .umask = 0x01,
   .event_name = "cpu_clk_thread_unhalted.ref_xclk",
   },
  {
   .event_code = {0x3C},
   .umask = 0x01,
   .event_name = "cpu_clk_thread_unhalted.ref_xclk_any",
   },
  {
   .event_code = {0x3c},
   .umask = 0x02,
   .event_name = "cpu_clk_thread_unhalted.one_thread_active",
   },
  {
   .event_code = {0x48},
   .umask = 0x01,
   .event_name = "l1d_pend_miss.pending",
   },
  {
   .event_code = {0x48},
   .umask = 0x01,
   .event_name = "l1d_pend_miss.pending_cycles",
   },
  {
   .event_code = {0x49},
   .umask = 0x01,
   .event_name = "dtlb_store_misses.miss_causes_a_walk",
   },
  {
   .event_code = {0x49},
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   .event_code = {0xb1},
   .umask = 0x02,
   .event_name = "uops_executed.core_cycles_ge_3",
   },
  {
   .event_code = {0xb1},
   .umask = 0x02,
   .event_name = "uops_executed.core_cycles_ge_4",
   },
  {
   .event_code = {0xb1},
   .umask = 0x02,
   .event_name = "uops_executed.core_cycles_none",
   },
  {
   .event_code = {0xb2},
   .umask = 0x01,
   .event_name = "offcore_requests_buffer.sq_full",
   },
  {
   .event_code = {0xBC},
   .umask = 0x11,
   .event_name = "page_walker_loads.dtlb_l1",
   },
  {
   .event_code = {0xBC},
   .umask = 0x12,
   .event_name = "page_walker_loads.dtlb_l2",
   },
  {
   .event_code = {0xBC},
   .umask = 0x14,
   .event_name = "page_walker_loads.dtlb_l3",
   },
  {
   .event_code = {0xBC},
   .umask = 0x18,
   .event_name = "page_walker_loads.dtlb_memory",
   },
  {
   .event_code = {0xBC},
   .umask = 0x21,
   .event_name = "page_walker_loads.itlb_l1",
   },
  {
   .event_code = {0xBC},
   .umask = 0x22,
   .event_name = "page_walker_loads.itlb_l2",
   },
  {
   .event_code = {0xBC},
   .umask = 0x24,
   .event_name = "page_walker_loads.itlb_l3",
   },
  {
   .event_code = {0xBD},
   .umask = 0x01,
   .event_name = "tlb_flush.dtlb_thread",
   },
  {
   .event_code = {0xBD},
   .umask = 0x20,
   .event_name = "tlb_flush.stlb_any",
   },
  {
   .event_code = {0xC0},
   .umask = 0x00,
   .event_name = "inst_retired.any_p",
   },
  {
   .event_code = {0xC0},
   .umask = 0x01,
   .event_name = "inst_retired.prec_dist",
   },
  {
   .event_code = {0xC0},
   .umask = 0x02,
   .event_name = "inst_retired.x87",
   },
  {
   .event_code = {0xC1},
   .umask = 0x08,
   .event_name = "other_assists.avx_to_sse",
   },
  {
   .event_code = {0xC1},
   .umask = 0x10,
   .event_name = "other_assists.sse_to_avx",
   },
  {
   .event_code = {0xC1},
   .umask = 0x40,
   .event_name = "other_assists.any_wb_assist",
   },
  {
   .event_code = {0xC2},
   .umask = 0x01,
   .event_name = "uops_retired.all",
   },
  {
   .event_code = {0xC2},
   .umask = 0x01,
   .event_name = "uops_retired.stall_cycles",
   },
  {
   .event_code = {0xC2},
   .umask = 0x01,
   .event_name = "uops_retired.total_cycles",
   },
  {
   .event_code = {0xC2},
   .umask = 0x02,
   .event_name = "uops_retired.retire_slots",
   },
  {
   .event_code = {0xC3},
   .umask = 0x01,
   .event_name = "machine_clears.cycles",
   },
  {
   .event_code = {0xC3},
   .umask = 0x01,
   .event_name = "machine_clears.count",
   },
  {
   .event_code = {0xC3},
   .umask = 0x02,
   .event_name = "machine_clears.memory_ordering",
   },
  {
   .event_code = {0xC3},
   .umask = 0x04,
   .event_name = "machine_clears.smc",
   },
  {
   .event_code = {0xC3},
   .umask = 0x20,
   .event_name = "machine_clears.maskmov",
   },
  {
   .event_code = {0xC4},
   .umask = 0x00,
   .event_name = "br_inst_retired.all_branches",
   },
  {
   .event_code = {0xC4},
   .umask = 0x01,
   .event_name = "br_inst_retired.conditional",
   },
  {
   .event_code = {0xC4},
   .umask = 0x02,
   .event_name = "br_inst_retired.near_call",
   },
  {
   .event_code = {0xC4},
   .umask = 0x02,
   .event_name = "br_inst_retired.near_call_r3",
   },
  {
   .event_code = {0xC4},
   .umask = 0x04,
   .event_name = "br_inst_retired.all_branches_pebs",
   },
  {
   .event_code = {0xC4},
   .umask = 0x08,
   .event_name = "br_inst_retired.near_return",
   },
  {
   .event_code = {0xC4},
   .umask = 0x10,
   .event_name = "br_inst_retired.not_taken",
   },
  {
   .event_code = {0xC4},
   .umask = 0x20,
   .event_name = "br_inst_retired.near_taken",
   },
  {
   .event_code = {0xC4},
   .umask = 0x40,
   .event_name = "br_inst_retired.far_branch",
   },
  {
   .event_code = {0xC5},
   .umask = 0x00,
   .event_name = "br_misp_retired.all_branches",
   },
  {
   .event_code = {0xC5},
   .umask = 0x01,
   .event_name = "br_misp_retired.conditional",
   },
  {
   .event_code = {0xC5},
   .umask = 0x04,
   .event_name = "br_misp_retired.all_branches_pebs",
   },
  {
   .event_code = {0xC5},
   .umask = 0x08,
   .event_name = "br_misp_retired.ret",
   },
  {
   .event_code = {0xC5},
   .umask = 0x20,
   .event_name = "br_misp_retired.near_taken",
   },
  {
   .event_code = {0xC7},
   .umask = 0x01,
   .event_name = "fp_arith_inst_retired.scalar_double",
   },
  {
   .event_code = {0xC7},
   .umask = 0x02,
   .event_name = "fp_arith_inst_retired.scalar_single",
   },
  {
   .event_code = {0xC7},
   .umask = 0x04,
   .event_name = "fp_arith_inst_retired.128b_packed_double",
   },
  {
   .event_code = {0xC7},
   .umask = 0x08,
   .event_name = "fp_arith_inst_retired.128b_packed_single",
   },
  {
   .event_code = {0xC7},
   .umask = 0x10,
   .event_name = "fp_arith_inst_retired.256b_packed_double",
   },
  {
   .event_code = {0xc7},
   .umask = 0x20,
   .event_name = "fp_arith_inst_retired.256b_packed_single",
   },
  {
   .event_code = {0xc8},
   .umask = 0x01,
   .event_name = "hle_retired.start",
   },
  {
   .event_code = {0xc8},
   .umask = 0x02,
   .event_name = "hle_retired.commit",
   },
  {
   .event_code = {0xc8},
   .umask = 0x04,
   .event_name = "hle_retired.aborted",
   },
  {
   .event_code = {0xc8},
   .umask = 0x08,
   .event_name = "hle_retired.aborted_misc1",
   },
  {
   .event_code = {0xc8},
   .umask = 0x10,
   .event_name = "hle_retired.aborted_misc2",
   },
  {
   .event_code = {0xc8},
   .umask = 0x20,
   .event_name = "hle_retired.aborted_misc3",
   },
  {
   .event_code = {0xc8},
   .umask = 0x40,
   .event_name = "hle_retired.aborted_misc4",
   },
  {
   .event_code = {0xc8},
   .umask = 0x80,
   .event_name = "hle_retired.aborted_misc5",
   },
  {
   .event_code = {0xc9},
   .umask = 0x01,
   .event_name = "rtm_retired.start",
   },
  {
   .event_code = {0xc9},
   .umask = 0x02,
   .event_name = "rtm_retired.commit",
   },
  {
   .event_code = {0xc9},
   .umask = 0x04,
   .event_name = "rtm_retired.aborted",
   },
  {
   .event_code = {0xc9},
   .umask = 0x08,
   .event_name = "rtm_retired.aborted_misc1",
   },
  {
   .event_code = {0xc9},
   .umask = 0x10,
   .event_name = "rtm_retired.aborted_misc2",
   },
  {
   .event_code = {0xc9},
   .umask = 0x20,
   .event_name = "rtm_retired.aborted_misc3",
   },
  {
   .event_code = {0xc9},
   .umask = 0x40,
   .event_name = "rtm_retired.aborted_misc4",
   },
  {
   .event_code = {0xc9},
   .umask = 0x80,
   .event_name = "rtm_retired.aborted_misc5",
   },
  {
   .event_code = {0xCA},
   .umask = 0x02,
   .event_name = "fp_assist.x87_output",
   },
  {
   .event_code = {0xCA},
   .umask = 0x04,
   .event_name = "fp_assist.x87_input",
   },
  {
   .event_code = {0xCA},
   .umask = 0x08,
   .event_name = "fp_assist.simd_output",
   },
  {
   .event_code = {0xCA},
   .umask = 0x10,
   .event_name = "fp_assist.simd_input",
   },
  {
   .event_code = {0xCA},
   .umask = 0x1E,
   .event_name = "fp_assist.any",
   },
  {
   .event_code = {0xCC},
   .umask = 0x20,
   .event_name = "rob_misc_events.lbr_inserts",
   },
  {
   .event_code = {0xD0},
   .umask = 0x11,
   .event_name = "mem_uops_retired.stlb_miss_loads",
   },
  {
   .event_code = {0xD0},
   .umask = 0x12,
   .event_name = "mem_uops_retired.stlb_miss_stores",
   },
  {
   .event_code = {0xD0},
   .umask = 0x21,
   .event_name = "mem_uops_retired.lock_loads",
   },
  {
   .event_code = {0xD0},
   .umask = 0x41,
   .event_name = "mem_uops_retired.split_loads",
   },
  {
   .event_code = {0xD0},
   .umask = 0x42,
   .event_name = "mem_uops_retired.split_stores",
   },
  {
   .event_code = {0xD0},
   .umask = 0x81,
   .event_name = "mem_uops_retired.all_loads",
   },
  {
   .event_code = {0xD0},
   .umask = 0x82,
   .event_name = "mem_uops_retired.all_stores",
   },
  {
   .event_code = {0xD1},
   .umask = 0x01,
   .event_name = "mem_load_uops_retired.l1_hit",
   },
  {
   .event_code = {0xD1},
   .umask = 0x02,
   .event_name = "mem_load_uops_retired.l2_hit",
   },
  {
   .event_code = {0xD1},
   .umask = 0x04,
   .event_name = "mem_load_uops_retired.l3_hit",
   },
  {
   .event_code = {0xD1},
   .umask = 0x08,
   .event_name = "mem_load_uops_retired.l1_miss",
   },
  {
   .event_code = {0xD1},
   .umask = 0x10,
   .event_name = "mem_load_uops_retired.l2_miss",
   },
  {
   .event_code = {0xD1},
   .umask = 0x20,
   .event_name = "mem_load_uops_retired.l3_miss",
   },
  {
   .event_code = {0xD1},
   .umask = 0x40,
   .event_name = "mem_load_uops_retired.hit_lfb",
   },
  {
   .event_code = {0xD2},
   .umask = 0x01,
   .event_name = "mem_load_uops_l3_hit_retired.xsnp_miss",
   },
  {
   .event_code = {0xD2},
   .umask = 0x02,
   .event_name = "mem_load_uops_l3_hit_retired.xsnp_hit",
   },
  {
   .event_code = {0xD2},
   .umask = 0x04,
   .event_name = "mem_load_uops_l3_hit_retired.xsnp_hitm",
   },
  {
   .event_code = {0xD2},
   .umask = 0x08,
   .event_name = "mem_load_uops_l3_hit_retired.xsnp_none",
   },
  {
   .event_code = {0xD3},
   .umask = 0x01,
   .event_name = "mem_load_uops_l3_miss_retired.local_dram",
   },
  {
   .event_code = {0xD3},
   .umask = 0x04,
   .event_name = "mem_load_uops_l3_miss_retired.remote_dram",
   },
  {
   .event_code = {0xD3},
   .umask = 0x10,
   .event_name = "mem_load_uops_l3_miss_retired.remote_hitm",
   },
  {
   .event_code = {0xD3},
   .umask = 0x20,
   .event_name = "mem_load_uops_l3_miss_retired.remote_fwd",
   },
  {
   .event_code = {0xe6},
   .umask = 0x1f,
   .event_name = "baclears.any",
   },
  {
   .event_code = {0xF0},
   .umask = 0x01,
   .event_name = "l2_trans.demand_data_rd",
   },
  {
   .event_code = {0xF0},
   .umask = 0x02,
   .event_name = "l2_trans.rfo",
   },
  {
   .event_code = {0xF0},
   .umask = 0x04,
   .event_name = "l2_trans.code_rd",
   },
  {
   .event_code = {0xF0},
   .umask = 0x08,
   .event_name = "l2_trans.all_pf",
   },
  {
   .event_code = {0xF0},
   .umask = 0x10,
   .event_name = "l2_trans.l1d_wb",
   },
  {
   .event_code = {0xF0},
   .umask = 0x20,
   .event_name = "l2_trans.l2_fill",
   },
  {
   .event_code = {0xF0},
   .umask = 0x40,
   .event_name = "l2_trans.l2_wb",
   },
  {
   .event_code = {0xF0},
   .umask = 0x80,
   .event_name = "l2_trans.all_requests",
   },
  {
   .event_code = {0xF1},
   .umask = 0x01,
   .event_name = "l2_lines_in.i",
   },
  {
   .event_code = {0xF1},
   .umask = 0x02,
   .event_name = "l2_lines_in.s",
   },
  {
   .event_code = {0xF1},
   .umask = 0x04,
   .event_name = "l2_lines_in.e",
   },
  {
   .event_code = {0xF1},
   .umask = 0x07,
   .event_name = "l2_lines_in.all",
   },
  {
   .event_code = {0xF2},
   .umask = 0x05,
   .event_name = "l2_lines_out.demand_clean",
   },
  {
   .event_code = {0xf4},
   .umask = 0x10,
   .event_name = "sq_misc.split_lock",
   },
  {
   .event_name = 0,
   },
};

PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);