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| author |   pmikus <pmikus@cisco.com> | 2021-06-15 07:57:50 +0000 |
|---|---|---|
| committer | Peter Mikus <pmikus@cisco.com> | 2021-06-15 08:05:28 +0000 |
| commit | 2072a56eeca53f00cff1b5d888d24f7271ae1fb4 (patch) | |
| tree | d59dece088a4b6a31245e6d73230da487bc55935 /docs/report/introduction/methodology_multi_core_speedup.rst | |
| parent | 6726e389d87ebd601a4f4d083833c9f04f573d75 (diff) | |
Report: Update Infra sections
Signed-off-by: pmikus <pmikus@cisco.com>
Change-Id: I14aa6f64b2621ad306e1cd79fafefe94dd1ed85a
Diffstat (limited to 'docs/report/introduction/methodology_multi_core_speedup.rst')
| -rw-r--r-- | docs/report/introduction/methodology_multi_core_speedup.rst | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/docs/report/introduction/methodology_multi_core_speedup.rst b/docs/report/introduction/methodology_multi_core_speedup.rst index 095f0f7796..05307549f4 100644 --- a/docs/report/introduction/methodology_multi_core_speedup.rst +++ b/docs/report/introduction/methodology_multi_core_speedup.rst @@ -14,8 +14,7 @@ applied in BIOS and requires server SUT reload for it to take effect, making it impractical for continuous changes of HT mode of operation. |csit-release| performance tests are executed with server SUTs' Intel -XEON processors configured with Intel Hyper-Threading Disabled for all -Xeon Haswell testbeds (3n-hsw) and with Intel Hyper-Threading Enabled +XEON processors configured with Intel Hyper-Threading Enabled for all Xeon Skylake and Xeon Cascadelake testbeds. More information about physical testbeds is provided in @@ -27,13 +26,6 @@ Multi-core Tests |csit-release| multi-core tests are executed in the following VPP worker thread and physical core configurations: -#. Intel Xeon Haswell testbeds (3n-hsw) with Intel HT disabled - (1 logical CPU core per each physical core): - - #. 1t1c - 1 VPP worker thread on 1 physical core. - #. 2t2c - 2 VPP worker threads on 2 physical cores. - #. 4t4c - 4 VPP worker threads on 4 physical cores. - #. Intel Xeon Skylake and Cascadelake testbeds (2n-skx, 3n-skx, 2n-clx) with Intel HT enabled (2 logical CPU cores per each physical core): |