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| author |   Tibor Frank <tifrank@cisco.com> | 2022-09-09 13:01:50 +0200 |
|---|---|---|
| committer | Tibor Frank <tifrank@cisco.com> | 2022-09-12 10:46:42 +0200 |
| commit | c2d12bb8aefc1b5dc856d2278d7ea81321f74c8f (patch) | |
| tree | 21aff0364113e29e2fec59f99d178e034e0f1a6f /docs/report/introduction/methodology_multi_core_speedup.rst | |
| parent | bd22f795e39ae4a548494340809069288b032d93 (diff) | |
Report: Remove skx testbeds
Change-Id: I638b899ad3a227c7702f6d8229c49ca0835da66b
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs/report/introduction/methodology_multi_core_speedup.rst')
| -rw-r--r-- | docs/report/introduction/methodology_multi_core_speedup.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/report/introduction/methodology_multi_core_speedup.rst b/docs/report/introduction/methodology_multi_core_speedup.rst index 05307549f4..d9515faf43 100644 --- a/docs/report/introduction/methodology_multi_core_speedup.rst +++ b/docs/report/introduction/methodology_multi_core_speedup.rst @@ -26,7 +26,7 @@ Multi-core Tests |csit-release| multi-core tests are executed in the following VPP worker thread and physical core configurations: -#. Intel Xeon Skylake and Cascadelake testbeds (2n-skx, 3n-skx, 2n-clx) +#. Intel Xeon Icelake and Cascadelake testbeds (2n-icx, 3n-icx, 2n-clx) with Intel HT enabled (2 logical CPU cores per each physical core): #. 2t1c - 2 VPP worker threads on 1 physical core. |