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author | 2022-06-14 11:14:49 +0000 | |
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committer | 2022-06-14 11:22:41 +0000 | |
commit | 614c812e640c6140fc30272ba4d9df2cb15258de (patch) | |
tree | 8012cf4fce78a02216d4fd7897d2a758846358ab /docs/report/introduction/test_environment_changes_vpp.rst | |
parent | 26ba8001fc1a9b1901d904e1fa36bd4298b37fca (diff) |
doc(report): Update test environment
Signed-off-by: Peter Mikus <pmikus@cisco.com>
Change-Id: I9987cac1493ea75eb097a0f2123768eec1ca3d73
(cherry picked from commit 1b97d7088f4db702b05c0fd4cbc02a52c97e4529)
Diffstat (limited to 'docs/report/introduction/test_environment_changes_vpp.rst')
-rw-r--r-- | docs/report/introduction/test_environment_changes_vpp.rst | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/report/introduction/test_environment_changes_vpp.rst b/docs/report/introduction/test_environment_changes_vpp.rst index 83a9eedffb..5f3d3bf3e9 100644 --- a/docs/report/introduction/test_environment_changes_vpp.rst +++ b/docs/report/introduction/test_environment_changes_vpp.rst @@ -17,8 +17,8 @@ topology types are used: - **2-Node Topology**: Consisting of one server acting as SUTs and one server as TG both connected in ring topology. -Tested SUT servers are based on a range of processors including Intel -Intel Xeon Skylake-SP, Intel Xeon Cascade Lake-SP, Arm, +Tested SUT servers are based on a range of processors including +Intel Xeon Icelake-SP, Intel Xeon Skylake-SP, Intel Xeon Cascade Lake-SP, Arm, Intel Atom. More detailed description is provided in :ref:`tested_physical_topologies`. Tested logical topologies are described in :ref:`tested_logical_topologies`. |