Report 2005: Add data, review graphs

Change-Id: I2913ed579369a26a1226cfbe958432d1b3e11789
Signed-off-by: Tibor Frank <tifrank@cisco.com>
(cherry picked from commit 12c3608c3464add7664e3b8f41b07b9b8fd03f1c)

1 files changed, 0 insertions, 27 deletions

diff --git a/docs/report/introduction/test_environment_intro.rst b/docs/report/introduction/test_environment_intro.rst
index da817f269d..7c4d5dfc9f 100644
--- a/docs/report/introduction/test_environment_intro.rst
+++ b/docs/report/introduction/test_environment_intro.rst
@@ -28,30 +28,3 @@ physical testbeds are maintained in FD.io CSIT repository:
 `FD.io CSIT testbeds - Xeon Cascade Lake`_,
 `FD.io CSIT testbeds - Xeon Skylake, Arm, Atom`_ and
 `FD.io CSIT Testbeds - Xeon Haswell`_.
-
-Pre-Test Server Calibration
----------------------------
-
-Number of SUT server sub-system runtime parameters have been identified
-as impacting data plane performance tests. Calibrating those parameters
-is part of FD.io CSIT pre-test activities, and includes measuring and
-reporting following:
-
-#. System level core jitter - measure duration of core interrupts by
-   Linux in clock cycles and how often interrupts happen. Using
-   `CPU core jitter tool <https://git.fd.io/pma_tools/tree/jitter>`_.
-
-#. Memory bandwidth - measure bandwidth with `Intel MLC tool
-   <https://software.intel.com/en-us/articles/intelr-memory-latency-checker>`_.
-
-#. Memory latency - measure memory latency with Intel MLC tool.
-
-#. Cache latency at all levels (L1, L2, and Last Level Cache) - measure
-   cache latency with Intel MLC tool.
-
-Measured values of listed parameters are especially important for
-repeatable zero packet loss throughput measurements across multiple
-system instances. Generally they come useful as a background data for
-comparing data plane performance results across disparate servers.
-
-Following sections include measured calibration data for testbeds.