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| author |   Tibor Frank <tifrank@cisco.com> | 2020-01-27 15:24:08 +0100 |
|---|---|---|
| committer | Tibor Frank <tifrank@cisco.com> | 2020-01-28 09:39:36 +0000 |
| commit | 6716e51e3a27cfd2850a399c9ccc2818c2038eaf (patch) | |
| tree | 5e943c0c5e1d8ed0ada2007ed42737309697b0ed /docs/report/introduction/test_environment_sut_calib_tsh.rst | |
| parent | f7452e826cd83fc5ded28c1268f6f4aab252ca2d (diff) | |
PAL: Add latency by percentile graph
Change-Id: I38c03e089fd709afc848ecec55474d5c6925a58e
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs/report/introduction/test_environment_sut_calib_tsh.rst')
| -rw-r--r-- | docs/report/introduction/test_environment_sut_calib_tsh.rst | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/docs/report/introduction/test_environment_sut_calib_tsh.rst b/docs/report/introduction/test_environment_sut_calib_tsh.rst index 139d30fd50..00447b9fd9 100644 --- a/docs/report/introduction/test_environment_sut_calib_tsh.rst +++ b/docs/report/introduction/test_environment_sut_calib_tsh.rst @@ -78,3 +78,5 @@ System-level Core Jitter 160022 169610 9588 160044 160022 173162 2580611072 3204390608 28 160022 169254 9232 160044 160022 173162 1492189184 3204399760 29 160022 169386 9364 160046 160022 173162 403767296 3204417762 30 + +.. include:: ../introduction/test_environment_sut_meltspec_tsh.rst |