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authorTibor Frank <tifrank@cisco.com>2018-05-29 10:45:47 +0200
committerTibor Frank <tifrank@cisco.com>2018-05-30 11:06:08 +0000
commite01470ec9038338409a494a2652eecabf4394578 (patch)
tree9a2e19441e2456652901b0e6438fdf909668f6fa /docs/report/vpp_performance_tests/packet_latency_graphs/srv6.rst
parent564c2ae4f2d3cc7a210f6fe17f55091afcc05d45 (diff)
CSIT-1105: Prepare and generate 18.01.2 report
Change-Id: Iebda4fd10701c27512b443c14b2aeef314003d58 Signed-off-by: Tibor Frank <tifrank@cisco.com>
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+SRv6
+====
+
+This section includes summary graphs of VPP Phy-to-Phy packet latency
+with SRv6 measured at 50% of discovered NDR throughput
+rate. Latency is reported for VPP running in multiple configurations of
+VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
+physical CPU core(s) placement.
+
+VPP packet latency in 1t1c setup (1thread, 1core) is presented in the graph below.
+
+.. raw:: html
+
+ <iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/78B-1t1c-ethip6-srv6-ndrdisc-lat50.html"></iframe>
+
+.. raw:: latex
+
+ \begin{figure}[H]
+ \centering
+ \graphicspath{{../_build/_static/vpp/}}
+ \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{78B-1t1c-ethip6-srv6-ndrdisc-lat50}
+ \label{fig:78B-1t1c-ethip6-srv6-ndrdisc-lat50}
+ \end{figure}
+
+*Figure 1. VPP 1thread 1core - packet latency for Phy-to-Phy SRv6.*
+
+CSIT source code for the test cases used for above plots can be found in
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/srv6?h=rls1804>`_.
+
+VPP packet latency in 2t2c setup (2thread, 2core) is presented in the graph below.
+
+.. raw:: html
+
+ <iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/78B-2t2c-ethip6-srv6-ndrdisc-lat50.html"></iframe>
+
+.. raw:: latex
+
+ \begin{figure}[H]
+ \centering
+ \graphicspath{{../_build/_static/vpp/}}
+ \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{78B-2t2c-ethip6-srv6-ndrdisc-lat50}
+ \label{fig:78B-2t2c-ethip6-srv6-ndrdisc-lat50}
+ \end{figure}
+
+*Figure 2. VPP 2threads 2cores - packet latency for Phy-to-Phy SRv6.*
+
+CSIT source code for the test cases used for above plots can be found in
+`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/srv6?h=rls1804>`_.