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| author |   Yulong Pei <yulong.pei@intel.com> | 2018-11-20 22:23:10 +0800 |
|---|---|---|
| committer |   Tibor Frank <tifrank@cisco.com> | 2018-11-21 11:03:15 +0000 |
| commit | f7db30b2763d674b7a0d3b690985d10f5f5be0d1 (patch) | |
| tree | a352d80072b26499d6d06a3829ec0328aa046ad1 /docs/report/vpp_performance_tests/test_environment.rst | |
| parent | 038eac9472666920a5fbdd8bb55e58bc8044ddc5 (diff) | |
doc: add calibration result and meltspec check result for Denverton
Change-Id: I0094ba5ea59b18d6a7a9235cd153db393517cc02
Signed-off-by: Yulong Pei <yulong.pei@intel.com>
Diffstat (limited to 'docs/report/vpp_performance_tests/test_environment.rst')
| -rw-r--r-- | docs/report/vpp_performance_tests/test_environment.rst | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/docs/report/vpp_performance_tests/test_environment.rst b/docs/report/vpp_performance_tests/test_environment.rst index 68dfa964df..a2676db056 100644 --- a/docs/report/vpp_performance_tests/test_environment.rst +++ b/docs/report/vpp_performance_tests/test_environment.rst @@ -9,6 +9,8 @@ .. include:: ../introduction/test_environment_sut_calib_skx.rst +.. include:: ../introduction/test_environment_sut_calib_dnv.rst + .. include:: ../introduction/test_environment_sut_conf_1.rst .. include:: ../introduction/test_environment_sut_conf_2.rst |