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author | Tibor Frank <tifrank@cisco.com> | 2023-02-09 14:05:25 +0100 |
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committer | Tibor Frank <tifrank@cisco.com> | 2023-02-09 13:07:39 +0000 |
commit | dafd553fcaca42cf4ac50108b0a4763091c17849 (patch) | |
tree | a4a0f6ed75d5898e11c14be063ac0811d8aaa45c /docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst | |
parent | a0009c05b2ced256a26444d965f9f8371badb034 (diff) |
Report: Set rls2302 in links
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Change-Id: I1fadafd89108c832e933e98632aad4de567de11e
(cherry picked from commit 7bd81f76b9c5b9dc3ab6a1df6156dac3fca16240)
Diffstat (limited to 'docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst')
-rw-r--r-- | docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst index bd78ff080a..64dba4d53d 100644 --- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst +++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/container_memif.rst @@ -15,7 +15,7 @@ running in multiple configurations of VPP worker thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls2210>`_. +`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/container_memif?h=rls2302>`_. .. toctree:: |