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| author |   Tibor Frank <tifrank@cisco.com> | 2021-09-29 13:07:03 +0200 |
|---|---|---|
| committer | Tibor Frank <tifrank@cisco.com> | 2021-09-29 14:25:34 +0000 |
| commit | 33eac7ac4d82c96dfac79bfe1bc6f7e06f3e3c47 (patch) | |
| tree | 7ab0d9c00f202f5a53f41b83a4152f5d5c1abf10 /docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst | |
| parent | eecc22d8782a562594d776e962a2fa952635bb5a (diff) | |
Report: configure rls2110
Change-Id: I0020d2f11bd027ef80bf77f2e30f9ea19a424aa1
Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst')
| -rw-r--r-- | docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst index 75a9322b63..957e7059da 100644 --- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst +++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/ipsec.rst @@ -17,7 +17,7 @@ VPP worker thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement. CSIT source code for the test cases used for plots can be found in -`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls2106>`_. +`CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls2110>`_. .. toctree:: |