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authorTibor Frank <tifrank@cisco.com>2018-11-21 14:59:34 +0100
committerTibor Frank <tifrank@cisco.com>2018-11-21 14:59:34 +0100
commit4d78abab08386eaea1e3ad4f00a50e8d1e2a57d5 (patch)
tree94e1baf7331b533899611f7ea4c0aae350eb68d3 /docs
parent32bb9cfcffcfbe6ec68d8469ebc8194580b31689 (diff)
Report: Fix the labels
Change-Id: I82740007b4c12b8a21014b4572b034013f165280 Signed-off-by: Tibor Frank <tifrank@cisco.com>
Diffstat (limited to 'docs')
-rw-r--r--docs/report/vpp_performance_tests/packet_latency_graphs/index.rst4
-rw-r--r--docs/report/vpp_performance_tests/packet_throughput_graphs/index.rst4
-rw-r--r--docs/report/vpp_performance_tests/test_environment.rst4
-rw-r--r--docs/report/vpp_performance_tests/throughput_speedup_multi_core/index.rst4
4 files changed, 8 insertions, 8 deletions
diff --git a/docs/report/vpp_performance_tests/packet_latency_graphs/index.rst b/docs/report/vpp_performance_tests/packet_latency_graphs/index.rst
index 1cf4c66106..c6c40d7a7d 100644
--- a/docs/report/vpp_performance_tests/packet_latency_graphs/index.rst
+++ b/docs/report/vpp_performance_tests/packet_latency_graphs/index.rst
@@ -1,10 +1,10 @@
-.. _VPP_Packet_Latency:
-
.. raw:: latex
\clearpage
+.. _VPP_Packet_Latency:
+
Packet Latency
==============
diff --git a/docs/report/vpp_performance_tests/packet_throughput_graphs/index.rst b/docs/report/vpp_performance_tests/packet_throughput_graphs/index.rst
index 688bdd23a4..9bc7184ba8 100644
--- a/docs/report/vpp_performance_tests/packet_throughput_graphs/index.rst
+++ b/docs/report/vpp_performance_tests/packet_throughput_graphs/index.rst
@@ -1,10 +1,10 @@
-.. _VPP_Packet_Throughput:
-
.. raw:: latex
\clearpage
+.. _VPP_Packet_Throughput:
+
Packet Throughput
=================
diff --git a/docs/report/vpp_performance_tests/test_environment.rst b/docs/report/vpp_performance_tests/test_environment.rst
index 7b1814164f..57e797339e 100644
--- a/docs/report/vpp_performance_tests/test_environment.rst
+++ b/docs/report/vpp_performance_tests/test_environment.rst
@@ -1,10 +1,10 @@
-.. _vpp_test_environment:
-
.. raw:: latex
\clearpage
+.. _vpp_test_environment:
+
.. include:: ../introduction/test_environment_intro.rst
.. include:: ../introduction/test_environment_sut_calib_hsw.rst
diff --git a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/index.rst b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/index.rst
index c56e55cc0e..b6feb2b8a6 100644
--- a/docs/report/vpp_performance_tests/throughput_speedup_multi_core/index.rst
+++ b/docs/report/vpp_performance_tests/throughput_speedup_multi_core/index.rst
@@ -1,10 +1,10 @@
-.. _throughput_speedup_multi_core:
-
.. raw:: latex
\clearpage
+.. _throughput_speedup_multi_core:
+
Speedup Multi-Core
==================