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| author |   Dave Barach <dave@barachs.net> | 2018-05-29 17:06:45 -0400 |
|---|---|---|
| committer |   Florin Coras <florin.coras@gmail.com> | 2018-06-04 22:24:48 +0000 |
| commit | 473f46135c3fd77dad5614215cc279b1164e9a74 (patch) | |
| tree | c77881bd8157ce9380d91e94b43463f6c9f712a0 /src/plugins | |
| parent | 1b25552ebb8f653d473bd58a3bf56499701c792d (diff) | |
Configure or deduce CLIB_LOG2_CACHE_LINE_BYTES (VPP-1064)
Added configure argument "--with-log2-cache-line-bytes=5|6|7|auto"
AKA 32, 64, or 128 bytes, or use the inferred value from the build host.
produces build-xxx/vpp/vppinfra/config.h, which .../src/vppinfra/cache.h
Kernels which implement the following pseudo-file (aka x86_64) are
easy: /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size
Otherwise, extract the cpuid from /proc/cpuinfo and map it to the
cache line size.
Change-Id: I7ff861e042faf82c3901fa1db98864fbdea95b74
Signed-off-by: Dave Barach <dave@barachs.net>
Signed-off-by: Nitin Saxena <nitin.saxena@cavium.com>
Diffstat (limited to 'src/plugins')
| -rw-r--r-- | src/plugins/dpdk/device/init.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/plugins/dpdk/device/init.c b/src/plugins/dpdk/device/init.c index b5a8e3bcd4b..ceaa5bb61e9 100644 --- a/src/plugins/dpdk/device/init.c +++ b/src/plugins/dpdk/device/init.c @@ -1691,6 +1691,8 @@ dpdk_init (vlib_main_t * vm) "Data in cache line 0 is bigger than cache line size"); STATIC_ASSERT (offsetof (frame_queue_trace_t, cacheline0) == 0, "Cache line marker must be 1st element in frame_queue_trace_t"); + STATIC_ASSERT (RTE_CACHE_LINE_SIZE == 1 << CLIB_LOG2_CACHE_LINE_BYTES, + "DPDK RTE CACHE LINE SIZE does not match with 1<<CLIB_LOG2_CACHE_LINE_BYTES"); dm->vlib_main = vm; dm->vnet_main = vnet_get_main (); |