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| author |   Damjan Marion <damarion@cisco.com> | 2020-04-29 21:28:15 +0200 |
|---|---|---|
| committer | Damjan Marion <damarion@cisco.com> | 2020-04-30 13:25:29 +0200 |
| commit | 162330f25aeec09694fffaaa31ba9b318620eb9c (patch) | |
| tree | 4c7a10aae7b2e5d54ef21260d08ad3671d44b061 /src/vppinfra/vector.h | |
| parent | dc0ded7dd7a6b8ee68df25cd56666de804e55e64 (diff) | |
build: rework x86 CPU variants
Type: improvement
Change-Id: Ief243f88e654e578ef9b8060fcf535b364aececb
Signed-off-by: Damjan Marion <damarion@cisco.com>
Diffstat (limited to 'src/vppinfra/vector.h')
| -rw-r--r-- | src/vppinfra/vector.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/vppinfra/vector.h b/src/vppinfra/vector.h index 906d8d8fbfd..8b08db22124 100644 --- a/src/vppinfra/vector.h +++ b/src/vppinfra/vector.h @@ -66,7 +66,7 @@ #endif #endif -#if defined (__AVX512F__) +#if defined (__AVX512BITALG__) #define CLIB_HAVE_VEC512 #endif @@ -168,7 +168,10 @@ typedef u64 u64x _vector_size (8); #include <vppinfra/vector_avx2.h> #endif -#if defined (__AVX512F__) +#if defined (__AVX512BITALG__) +/* Due to power level transition issues, we don't preffer AVX-512 on + Skylake X and CascadeLake CPUs, AVX512BITALG is introduced on + icelake CPUs */ #include <vppinfra/vector_avx512.h> #endif |