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authorDave Barach <dave@barachs.net>2018-05-29 17:06:45 -0400
committerFlorin Coras <florin.coras@gmail.com>2018-06-04 22:24:48 +0000
commit473f46135c3fd77dad5614215cc279b1164e9a74 (patch)
treec77881bd8157ce9380d91e94b43463f6c9f712a0 /src/vppinfra
parent1b25552ebb8f653d473bd58a3bf56499701c792d (diff)
Configure or deduce CLIB_LOG2_CACHE_LINE_BYTES (VPP-1064)
Added configure argument "--with-log2-cache-line-bytes=5|6|7|auto" AKA 32, 64, or 128 bytes, or use the inferred value from the build host. produces build-xxx/vpp/vppinfra/config.h, which .../src/vppinfra/cache.h Kernels which implement the following pseudo-file (aka x86_64) are easy: /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size Otherwise, extract the cpuid from /proc/cpuinfo and map it to the cache line size. Change-Id: I7ff861e042faf82c3901fa1db98864fbdea95b74 Signed-off-by: Dave Barach <dave@barachs.net> Signed-off-by: Nitin Saxena <nitin.saxena@cavium.com>
Diffstat (limited to 'src/vppinfra')
-rw-r--r--src/vppinfra/cache.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/vppinfra/cache.h b/src/vppinfra/cache.h
index e5c678eb517..ac0835523cb 100644
--- a/src/vppinfra/cache.h
+++ b/src/vppinfra/cache.h
@@ -41,10 +41,13 @@
#include <vppinfra/error_bootstrap.h>
/*
- * Allow CFLAGS to override the arch-specific cache line size
+ * Allow CFLAGS to override the configured / deduced cache line size
*/
#ifndef CLIB_LOG2_CACHE_LINE_BYTES
+/* defines CLIB_LOG2_CACHE_LINE_BYTES */
+#include <vppinfra/config.h>
+
/* Default cache line size of 64 bytes. */
#ifndef CLIB_LOG2_CACHE_LINE_BYTES
#define CLIB_LOG2_CACHE_LINE_BYTES 6