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authorNitin Saxena <nsaxena@marvell.com>2020-08-25 19:58:37 +0530
committerDamjan Marion <dmarion@me.com>2020-08-27 09:57:02 +0000
commite2f5236dc521f64c8ea08dc84893ff81f9ac7232 (patch)
tree680ba0aed1969711a4a0958894a8f1e28014b96c /src/vppinfra
parented04407829728c5d258b6600155edabd5198d971 (diff)
vppinfra: Multiarch support for OCTEONTX2 SoC
Type: feature - Added multiarch support for Marvell OCTEONTX2 - Corrected Marvell THUNDERX2 spelling Signed-off-by: Nitin Saxena <nsaxena@marvell.com> Change-Id: I42d3654aeda89759a2db9d695592ee3227b26c2b
Diffstat (limited to 'src/vppinfra')
-rw-r--r--src/vppinfra/cpu.h20
1 files changed, 16 insertions, 4 deletions
diff --git a/src/vppinfra/cpu.h b/src/vppinfra/cpu.h
index dc73c90ca34..750b3934df9 100644
--- a/src/vppinfra/cpu.h
+++ b/src/vppinfra/cpu.h
@@ -327,8 +327,10 @@ clib_cpu_part ()
return part;
}
-#define AARCH64_CPU_IMPLEMENTER_THUNERDERX2 0x43
-#define AARCH64_CPU_PART_THUNERDERX2 0x0af
+#define AARCH64_CPU_IMPLEMENTER_CAVIUM 0x43
+#define AARCH64_CPU_PART_THUNDERX2 0x0af
+#define AARCH64_CPU_PART_OCTEONTX2T96 0x0b2
+#define AARCH64_CPU_PART_OCTEONTX2T98 0x0b1
#define AARCH64_CPU_IMPLEMENTER_QDF24XX 0x51
#define AARCH64_CPU_PART_QDF24XX 0xc00
#define AARCH64_CPU_IMPLEMENTER_CORTEXA72 0x41
@@ -337,10 +339,20 @@ clib_cpu_part ()
#define AARCH64_CPU_PART_NEOVERSEN1 0xd0c
static inline int
+clib_cpu_march_priority_octeontx2 ()
+{
+ if ((AARCH64_CPU_IMPLEMENTER_CAVIUM == clib_cpu_implementer ()) &&
+ ((AARCH64_CPU_PART_OCTEONTX2T96 == clib_cpu_part ())
+ || AARCH64_CPU_PART_OCTEONTX2T98 == clib_cpu_part ()))
+ return 20;
+ return -1;
+}
+
+static inline int
clib_cpu_march_priority_thunderx2t99 ()
{
- if ((AARCH64_CPU_IMPLEMENTER_THUNERDERX2 == clib_cpu_implementer ()) &&
- (AARCH64_CPU_PART_THUNERDERX2 == clib_cpu_part ()))
+ if ((AARCH64_CPU_IMPLEMENTER_CAVIUM == clib_cpu_implementer ()) &&
+ (AARCH64_CPU_PART_THUNDERX2 == clib_cpu_part ()))
return 20;
return -1;
}