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authorDamjan Marion <damarion@cisco.com>2016-11-24 22:20:05 +0100
committerNeale Ranns <nranns@cisco.com>2016-11-25 09:27:31 +0000
commit30230dd7f854e77008b257c8be1de648e473338e (patch)
tree53e99fc7b066593ae9672cfbb80511362c53b450 /vnet
parent23a7412bda2c14b21deda66bc5555c9ee680dec8 (diff)
l2: fix latency issue casued by unnecesary read of previous cacheline
In majority of cases ethernet header sits at the beggining of cacheline. Reading (dst_mac - 2) into 64 bit register is much more expensive than doing simple bitwise shift, specially if previous cacheline is not prefetched. Change-Id: I35e53eae735098fb917a87c307e60a87e76e460f Signed-off-by: Damjan Marion <damarion@cisco.com>
Diffstat (limited to 'vnet')
-rw-r--r--vnet/vnet/l2/l2_fib.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/vnet/vnet/l2/l2_fib.h b/vnet/vnet/l2/l2_fib.h
index 8e7a52e4d02..63f394cfd44 100644
--- a/vnet/vnet/l2/l2_fib.h
+++ b/vnet/vnet/l2/l2_fib.h
@@ -105,7 +105,7 @@ l2fib_make_key (u8 * mac_address, u16 bd_index)
* Create the in-register key as F:E:D:C:B:A:H:L
* In memory the key is L:H:A:B:C:D:E:F
*/
- temp = *((u64 *) (mac_address - 2));
+ temp = *((u64 *) (mac_address)) << 16;
temp = (temp & ~0xffff) | (u64) (bd_index);
#else
/*