diff options
Diffstat (limited to 'build/external/patches/dpdk_21.11')
3 files changed, 219 insertions, 0 deletions
diff --git a/build/external/patches/dpdk_21.11/0001-common-qat-add-gen4-b-support.patch b/build/external/patches/dpdk_21.11/0001-common-qat-add-gen4-b-support.patch new file mode 100644 index 00000000000..3bb1430883f --- /dev/null +++ b/build/external/patches/dpdk_21.11/0001-common-qat-add-gen4-b-support.patch @@ -0,0 +1,35 @@ +From 939eb3d245e794679abc3c90be035e073a756b78 Mon Sep 17 00:00:00 2001 +From: Fan Zhang <roy.fan.zhang@intel.com> +Date: Thu, 13 Jan 2022 09:44:46 +0000 +Subject: [PATCH] common/qat: add gen4 b support + +Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> +--- + drivers/common/qat/qat_device.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c +index 437996f2e8..1f870d689a 100644 +--- a/drivers/common/qat/qat_device.c ++++ b/drivers/common/qat/qat_device.c +@@ -47,6 +47,9 @@ static const struct rte_pci_id pci_id_qat_map[] = { + { + RTE_PCI_DEVICE(0x8086, 0x4941), + }, ++ { ++ RTE_PCI_DEVICE(0x8086, 0x4943), ++ }, + {.device_id = 0}, + }; + +@@ -192,6 +195,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev, + qat_dev_gen = QAT_GEN3; + break; + case 0x4941: ++ case 0x4943: + qat_dev_gen = QAT_GEN4; + break; + default: +-- +2.25.1 + diff --git a/build/external/patches/dpdk_21.11/0001-net-igc-Add-device-ID-for-i226v.patch b/build/external/patches/dpdk_21.11/0001-net-igc-Add-device-ID-for-i226v.patch new file mode 100644 index 00000000000..f499136bba4 --- /dev/null +++ b/build/external/patches/dpdk_21.11/0001-net-igc-Add-device-ID-for-i226v.patch @@ -0,0 +1,137 @@ +From f4192afd7712a8d6be1e80af7478a12caaaa8917 Mon Sep 17 00:00:00 2001 +From: Matthew Smith <mgsmith@netgate.com> +Date: Fri, 25 Feb 2022 16:15:40 -0600 +Subject: [PATCH] net/igc: Add device ID for i226v + +Add the device ID 0x125C in order to enable the i226v. +Add phy ID for the i226 and allow that ID anywhere the phy ID for the +i225 was allowed. +--- + drivers/net/igc/base/igc_api.c | 1 + + drivers/net/igc/base/igc_defines.h | 1 + + drivers/net/igc/base/igc_hw.h | 1 + + drivers/net/igc/base/igc_i225.c | 1 + + drivers/net/igc/base/igc_phy.c | 11 ++++++----- + drivers/net/igc/igc_ethdev.c | 1 + + 6 files changed, 11 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/igc/base/igc_api.c b/drivers/net/igc/base/igc_api.c +index 2f8c0753cb..da51ef2d59 100644 +--- a/drivers/net/igc/base/igc_api.c ++++ b/drivers/net/igc/base/igc_api.c +@@ -888,6 +888,7 @@ s32 igc_set_mac_type(struct igc_hw *hw) + case IGC_DEV_ID_I225_I: + case IGC_DEV_ID_I220_V: + case IGC_DEV_ID_I225_BLANK_NVM: ++ case IGC_DEV_ID_I226_V: + mac->type = igc_i225; + break; + case IGC_DEV_ID_I350_VF: +diff --git a/drivers/net/igc/base/igc_defines.h b/drivers/net/igc/base/igc_defines.h +index 30a41300f5..767587a171 100644 +--- a/drivers/net/igc/base/igc_defines.h ++++ b/drivers/net/igc/base/igc_defines.h +@@ -1351,6 +1351,7 @@ + #define IGP04IGC_E_PHY_ID 0x02A80391 + #define M88_VENDOR 0x0141 + #define I225_I_PHY_ID 0x67C9DC00 ++#define I226_I_PHY_ID 0x67C9DC10 + + /* M88E1000 Specific Registers */ + #define M88IGC_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ +diff --git a/drivers/net/igc/base/igc_hw.h b/drivers/net/igc/base/igc_hw.h +index be38fafa5f..686fb721af 100644 +--- a/drivers/net/igc/base/igc_hw.h ++++ b/drivers/net/igc/base/igc_hw.h +@@ -164,6 +164,7 @@ struct igc_hw; + #define IGC_DEV_ID_I225_V 0x15F3 + #define IGC_DEV_ID_I225_K 0x3100 + #define IGC_DEV_ID_I225_I 0x15F8 ++#define IGC_DEV_ID_I226_V 0x125C + #define IGC_DEV_ID_I220_V 0x15F7 + #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD + #define IGC_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 +diff --git a/drivers/net/igc/base/igc_i225.c b/drivers/net/igc/base/igc_i225.c +index 060b2f8f93..8c078029f7 100644 +--- a/drivers/net/igc/base/igc_i225.c ++++ b/drivers/net/igc/base/igc_i225.c +@@ -176,6 +176,7 @@ static s32 igc_init_phy_params_i225(struct igc_hw *hw) + /* Verify phy id and set remaining function pointers */ + switch (phy->id) { + case I225_I_PHY_ID: ++ case I226_I_PHY_ID: + phy->type = igc_phy_i225; + phy->ops.set_d0_lplu_state = igc_set_d0_lplu_state_i225; + phy->ops.set_d3_lplu_state = igc_set_d3_lplu_state_i225; +diff --git a/drivers/net/igc/base/igc_phy.c b/drivers/net/igc/base/igc_phy.c +index 43bbe69bca..d46a6b3555 100644 +--- a/drivers/net/igc/base/igc_phy.c ++++ b/drivers/net/igc/base/igc_phy.c +@@ -1474,8 +1474,7 @@ s32 igc_phy_setup_autoneg(struct igc_hw *hw) + return ret_val; + } + +- if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && +- hw->phy.id == I225_I_PHY_ID) { ++ if (phy->autoneg_mask & ADVERTISE_2500_FULL) { + /* Read the MULTI GBT AN Control Register - reg 7.32 */ + ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << + MMD_DEVADDR_SHIFT) | +@@ -1615,8 +1614,7 @@ s32 igc_phy_setup_autoneg(struct igc_hw *hw) + ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, + mii_1000t_ctrl_reg); + +- if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && +- hw->phy.id == I225_I_PHY_ID) ++ if (phy->autoneg_mask & ADVERTISE_2500_FULL) + ret_val = phy->ops.write_reg(hw, + (STANDARD_AN_REG_MASK << + MMD_DEVADDR_SHIFT) | +@@ -1882,6 +1880,7 @@ s32 igc_phy_force_speed_duplex_m88(struct igc_hw *hw) + /* fall-through */ + case I225_I_PHY_ID: + /* fall-through */ ++ case I226_I_PHY_ID: + reset_dsp = false; + break; + default: +@@ -1923,7 +1922,7 @@ s32 igc_phy_force_speed_duplex_m88(struct igc_hw *hw) + return IGC_SUCCESS; + if (hw->phy.id == I210_I_PHY_ID) + return IGC_SUCCESS; +- if (hw->phy.id == I225_I_PHY_ID) ++ if (hw->phy.type == igc_phy_i225) + return IGC_SUCCESS; + if (hw->phy.id == M88E1543_E_PHY_ID || hw->phy.id == M88E1512_E_PHY_ID) + return IGC_SUCCESS; +@@ -2480,6 +2479,7 @@ s32 igc_get_cable_length_m88_gen2(struct igc_hw *hw) + phy->cable_length = phy_data / (is_cm ? 100 : 1); + break; + case I225_I_PHY_ID: ++ case I226_I_PHY_ID: + if (ret_val) + return ret_val; + /* TODO - complete with Foxville data */ +@@ -3064,6 +3064,7 @@ enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id) + phy_type = igc_phy_i210; + break; + case I225_I_PHY_ID: ++ case I226_I_PHY_ID: + phy_type = igc_phy_i225; + break; + default: +diff --git a/drivers/net/igc/igc_ethdev.c b/drivers/net/igc/igc_ethdev.c +index a1f1a9772b..0dd3a212d7 100644 +--- a/drivers/net/igc/igc_ethdev.c ++++ b/drivers/net/igc/igc_ethdev.c +@@ -97,6 +97,7 @@ static const struct rte_pci_id pci_id_igc_map[] = { + { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_V) }, + { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_I) }, + { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_K) }, ++ { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I226_V) }, + { .vendor_id = 0, /* sentinel */ }, + }; + +-- +2.30.1 (Apple Git-130) + diff --git a/build/external/patches/dpdk_21.11/0002-crypto-qat-fix-raw-data-path-aead.patch b/build/external/patches/dpdk_21.11/0002-crypto-qat-fix-raw-data-path-aead.patch new file mode 100644 index 00000000000..5e74f26c359 --- /dev/null +++ b/build/external/patches/dpdk_21.11/0002-crypto-qat-fix-raw-data-path-aead.patch @@ -0,0 +1,47 @@ +From 27c5c59aaf29236ba178ad18e399d3d6d9574739 Mon Sep 17 00:00:00 2001 +From: Fan Zhang <roy.fan.zhang@intel.com> +Date: Mon, 17 Jan 2022 15:22:18 +0000 +Subject: [PATCH] crypto/qat: fix raw data path aead + +This patch fixes raw data path AEAD operation for 4th QAT +generation. + +Fixes: 328d690d2f60 ("crypto/qat: update raw data path") + +Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> +--- + drivers/crypto/qat/qat_sym_hw_dp.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/qat/qat_sym_hw_dp.c b/drivers/crypto/qat/qat_sym_hw_dp.c +index 12825e448b..02875b822e 100644 +--- a/drivers/crypto/qat/qat_sym_hw_dp.c ++++ b/drivers/crypto/qat/qat_sym_hw_dp.c +@@ -520,6 +520,8 @@ enqueue_one_aead_job(struct qat_sym_session *ctx, + { + struct icp_qat_fw_la_cipher_req_params *cipher_param = + (void *)&req->serv_specif_rqpars; ++ struct icp_qat_fw_la_cipher_20_req_params *cipher_param20 = ++ (void *)&req->serv_specif_rqpars; + struct icp_qat_fw_la_auth_req_params *auth_param = + (void *)((uint8_t *)&req->serv_specif_rqpars + + ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET); +@@ -533,8 +535,13 @@ enqueue_one_aead_job(struct qat_sym_session *ctx, + /* CPM 1.7 uses single pass to treat AEAD as cipher operation */ + if (ctx->is_single_pass) { + enqueue_one_cipher_job(ctx, req, iv, ofs, data_len); +- cipher_param->spc_aad_addr = aad->iova; +- cipher_param->spc_auth_res_addr = digest->iova; ++ if (ctx->is_ucs) { ++ cipher_param20->spc_aad_addr = aad->iova; ++ cipher_param20->spc_auth_res_addr = digest->iova; ++ } else { ++ cipher_param->spc_aad_addr = aad->iova; ++ cipher_param->spc_auth_res_addr = digest->iova; ++ } + return; + } + +-- +2.25.1 + |