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-rw-r--r--docs/overview/performance/index.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/overview/performance/index.rst b/docs/overview/performance/index.rst
index 1c250206fcf..25e3897ff37 100644
--- a/docs/overview/performance/index.rst
+++ b/docs/overview/performance/index.rst
@@ -27,7 +27,7 @@ These features have been designed to take full advantage of common micro-process
* Reducing cache and TLS misses by processing packets in vectors
* Realizing `IPC <https://en.wikipedia.org/wiki/Instructions_per_cycle>`_ gains with vector instructions such as: SSE, AVX and NEON
* Eliminating mode switching, context switches and blocking, to always be doing useful work
-* Cache-lined aliged buffers for cache and memory efficiency
+* Cache-lined aligned buffers for cache and memory efficiency
Packet Throughput Graphs