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AgeCommit message (Expand)AuthorFilesLines
2016-02-11validate_type for easier type checks, hltapi move to trex_stl_libYaroslav Brustinov1-1007/+0
2016-02-10update hltapi + functional regression + remove old packet_builder testsYaroslav Brustinov1-98/+294
2016-02-09minor fixesimarom1-6/+17
2016-02-08first refactorimarom4-3307/+0
2016-02-05HLTAPI update + HLT packet builder functional tests (no simulation)Yaroslav Brustinov1-210/+400
2016-02-04add udp_pkt.py exampleHanoh Haim2-3/+10
2016-02-04add stl-sim -f optionHanoh Haim1-2/+4
2016-02-04Merge simulation fixHanoh Haim2-4/+3
2016-02-04fix simulation trim instructionHanoh Haim1-1/+1
2016-02-04add yaml for older pythonHanoh Haim1-29/+30
2016-02-03integration with scapyimarom2-4/+3
2016-02-02Fix Dan's packet builder payload_gen reference to packet, HLTAPI updated for ...Yaroslav Brustinov1-98/+107
2016-02-01fix for http://trex-tgn.cisco.com/youtrack/issue/trex-174imarom2-17/+26
2016-02-01HTLAPI updateYaroslav Brustinov2-82/+155
2016-02-01simulator support (API and profiles)imarom1-68/+189
2016-01-31add driver for Ubuntu 14.04.3, remove seconds from regression start time at H...Yaroslav Brustinov2-120/+130
2016-01-28HLTAPI updates, aggregated results tests count printYaroslav Brustinov1-182/+386
2016-01-28added API: release, remove_streamimarom2-30/+111
2016-01-27API: example for bi-directional flowsimarom1-5/+14
2016-01-26packet is now base64 encodedimarom2-4/+3
2016-01-26API simplification and exampleimarom2-97/+40
2016-01-26API cleaning upimarom2-242/+413
2016-01-24stateless sim was brokenimarom1-1/+2
2016-01-24added support for L1 B/W checkimarom2-17/+20
2016-01-24fixed issue trex-172: Console -m 100% is L2 and no L1imarom2-28/+38
2016-01-24added exampleimarom2-6/+9
2016-01-21phase 4imarom2-241/+173
2016-01-21draft #3imarom3-157/+335
2016-01-21draft #2imarom1-452/+604
2016-01-21highly draft - just backing upimarom2-513/+765
2016-01-21async publish nowimarom2-11/+53
2016-01-21draft of test API for statelessimarom1-82/+116
2016-01-18regression:Yaroslav Brustinov1-2/+5
2016-01-13-a is not mandatory anymore for every port's commandsimarom1-0/+1
2016-01-12perfectionist's job is never done - fixed the console prompt redraw whenimarom1-4/+15
2016-01-12some modifactions to the TUIimarom2-15/+4
2016-01-11small problem in the stl simulationimarom1-4/+3
2016-01-08minor updatesDan Klein1-9/+13
2016-01-08Merge branch 'dan_stateless'Dan Klein2-16/+97
2016-01-07Working version of streams view in TRex console.Dan Klein2-16/+97
2016-01-07first bug caught by the simulator - memory leakimarom1-7/+17
2016-01-07yet another stateless simulation phaseimarom1-1/+7
2016-01-07more options to the stateless simulationimarom1-58/+84
2016-01-05stateless sim - core_index and all cores simulationimarom1-7/+70
2016-01-05Merge remote-tracking branch 'origin/master'Yaroslav Brustinov1-0/+202
2016-01-05move regression to trex-coreYaroslav Brustinov1-40/+51
2016-01-04some additions to the stateless simulation modeimarom1-3/+29
2016-01-04a script to inject simulation stateless filesimarom1-0/+176
2015-12-21trex_client.py: maximal latency should not include c-max-*, only max-*Yaroslav Brustinov1-2/+2
2015-12-21latency.cpp: update ports stats at CLatencyManager::update, instead of CCPort...Yaroslav Brustinov1-0/+63