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-rw-r--r--src/plugins/perfmon/intel/bundle/iio_bw.c4
-rw-r--r--src/vlib/linux/pci.c2
-rw-r--r--src/vlib/pci/pci.c2
3 files changed, 3 insertions, 5 deletions
diff --git a/src/plugins/perfmon/intel/bundle/iio_bw.c b/src/plugins/perfmon/intel/bundle/iio_bw.c
index 64ec059c211..9aaca42233f 100644
--- a/src/plugins/perfmon/intel/bundle/iio_bw.c
+++ b/src/plugins/perfmon/intel/bundle/iio_bw.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 Cisco and/or its affiliates.
+ * Copyright (c) 2021 Intel and/or its affiliates.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
@@ -127,8 +127,6 @@ format_stack_socket (u8 *s, va_list *va)
uword *pu = hash_get (h, root_bus.bus);
e = pool_elt_at_index (p, (index_t) pu[0]);
- if (!e)
- return s;
s = format (s, "IIO%u/%u", e->socket_id, e->iio_unit_id);
return s;
diff --git a/src/vlib/linux/pci.c b/src/vlib/linux/pci.c
index 66787992209..e049b239f48 100644
--- a/src/vlib/linux/pci.c
+++ b/src/vlib/linux/pci.c
@@ -389,7 +389,7 @@ vlib_pci_get_device_root_bus (vlib_pci_addr_t *addr, vlib_pci_addr_t *root_bus)
{
u8 *rel_path = 0, *abs_path = 0, *link_path = 0;
unformat_input_t input;
- u32 fd = open (sysfs_pci_dev_path, O_RDONLY);
+ int fd = open (sysfs_pci_dev_path, O_RDONLY);
u32 size = 0;
u32 domain = 0, bus;
clib_error_t *err = NULL;
diff --git a/src/vlib/pci/pci.c b/src/vlib/pci/pci.c
index 5535eb1709c..249a26b1d21 100644
--- a/src/vlib/pci/pci.c
+++ b/src/vlib/pci/pci.c
@@ -158,7 +158,7 @@ format_vlib_pci_link_port (u8 *s, va_list *va)
if (!r)
return format (s, "unknown");
- return format (s, "P%d", r->link_status >> 24);
+ return format (s, "P%d", r->link_capabilities >> 24);
}
u8 *